From 11489454be1aef4cee4970e50ebf6133492363a6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 Jan 2022 17:32:46 +0000 Subject: [PATCH] double the number of lines in the L1 D/I-Cache to match microwatt early tests halved the number of lines so as to reduce the size of SRAMs but the issue is that this is mis-matched against the microwatt.dts device-tree file --- src/soc/experiment/dcache.py | 2 +- src/soc/experiment/icache.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 6d2d3cf2..a828e3c3 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -68,7 +68,7 @@ from nmutil.util import wrap # TODO: make these parameters of DCache at some point LINE_SIZE = 64 # Line size in bytes -NUM_LINES = 16 # Number of lines in a set +NUM_LINES = 32 # Number of lines in a set NUM_WAYS = 4 # Number of ways TLB_SET_SIZE = 64 # L1 DTLB entries per set TLB_NUM_WAYS = 2 # L1 DTLB number of sets diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 5417c8b3..8010bf2e 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -72,7 +72,7 @@ LINE_SIZE = 64 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits) ROW_SIZE = WB_DATA_BITS // 8 # Number of lines in a set -NUM_LINES = 16 +NUM_LINES = 32 # Number of ways NUM_WAYS = 4 # L1 ITLB number of entries (direct mapped) -- 2.30.2