From 115eebe2bb53bef0051e26e7be50fc8bc3e06f53 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jul 2019 12:43:38 +0100 Subject: [PATCH] remove "fail" in test --- src/ieee754/div_rem_sqrt_rsqrt/test_core.py | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py index 6a174ce2..3d58d0de 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py @@ -186,7 +186,6 @@ class TestDivPipeCore(unittest.TestCase): vl = rtlil.convert(dut, ports=[*dut.i, *dut.o]) with open(f"{base_name}.il", "w") as f: f.write(vl) - self.fail("generated invalid rtlil") # FIXME: remove when fixed dut = DivPipeCoreTestPipeline(core_config) with Simulator(dut, vcd_file=f"{base_name}.vcd", -- 2.30.2