From 1161c8fe093ff9aed586644dd4eb08c2486026e9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 Oct 2022 14:14:48 +0100 Subject: [PATCH] clarify notes on fishmv being R-M-W --- openpower/sv/rfc/ls002.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn index 096da9a3a..b71f35029 100644 --- a/openpower/sv/rfc/ls002.mdwn +++ b/openpower/sv/rfc/ls002.mdwn @@ -71,9 +71,10 @@ and TLB lookup. Even clearing an FPR to zero presently requires Load. lookups are mentioned for completeness but not included as part of this RFC. Another Stakeholder with a vested interest in 64-bit Prefixed instructions may wish to consider submitting them. -4. `fishmv` as a Read-Modify-Write saves five potential bits, making - the difference between a VA/DX-Form and requiring an entire Major - Opcode. +4. `fishmv` as a FRS-only Read-Modify-Write (instead of an unnecessary + FRS,FRA pair) saves five potential bits, making + the difference between a 5-bit XO (VA/DX-Form) and requiring an entire + Primary Opcode. **Changes** -- 2.30.2