From 1173e46e1200da2bd83b600835f8fd2618675cac Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Jun 2022 12:51:59 +0100 Subject: [PATCH] --- openpower/sv/remap.mdwn | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index 8f545b74e..1d10b4174 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -235,18 +235,26 @@ Fields: | 0b0010 | DCT Inner butterfly, pre-calculated coefficients | | 0b0011 | DCT Outer butterfly | | 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) | -| 0b0101 | DCT COS table generation | +| 0b0101 | DCT COS table index generation | | 0b0110 | DCT half-swap | | 0b0111 | reserved | -| 0b1000 | Indexed | -| 0b1001 | reserved | +| 0b1000 | Indexed (XY straight) | +| 0b1001 | Indexed (YX swapped) | | 0b1010 | iDCT Inner butterfly, pre-calculated coefficients | | 0b1011 | iDCT Outer butterfly | | 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) | -| 0b1101 | iDCT COS table generation | +| 0b1101 | iDCT COS table index generation | | 0b1110 | iDCT half-swap | | 0b1111 | FFT half-swap | +Examples showing how all of these Modes operate exists in the online +[SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD) + +`svshape` has *limited applicability* due to being a 32-bit instruction. +The full capability of SVSHAPE SPRs may be accessed by directly writing +to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions +larger than 32, and in-place Transpose. Potentially a future v3.1 Prefixed +instruction, `psvshape`, may extend the capability here. # 4x4 Matrix to vec4 Multiply Example -- 2.30.2