From 11b8ddcc73fe24a047820a60b6767698cd363517 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Apr 2022 15:52:07 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 2347ed6cf..f1ba46b60 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -64,7 +64,8 @@ even if the branch points to the next instruction (no actual branch). # Overview -When considering an "array" of branch-tests, there are four useful modes: +When considering an "array" of branch-tests, there are four +primarily-useful modes: AND, OR, NAND and NOR of all Conditions. NAND and NOR may be synthesised from AND and OR by inverting `BO[1]` which just leaves two modes: @@ -429,8 +430,16 @@ should **not** be considered part of the Vector. Consequently: # Boolean Logic combinations -There are an extraordinary number of different combinations which -provide completely different and useful behaviour. +In a Scalar ISA, Branch-Conditional testing even of vector +results may be performed through inversion of tests. NOR of +all tests may be performed by inversion of the scalar condition +and branching *out* from the scalar loop around elements, +using scalar operations. + +In a parallel (Vector) ISA it is the ISA itself which must perform +the prerequisite logic manipulation. +Thus for SVP64 there are an extraordinary number of nesessary combinations +which provide completely different and useful behaviour. Available options to combine: * `BO[0]` to make an unconditional branch would seem irrelevant if -- 2.30.2