From 11c6d557e4f3716ae82a8901915dd1a523409090 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 19 Mar 2022 22:44:36 +0000 Subject: [PATCH] add VERSA_ECP5 85F custom board --- hyperram_model/README.txt | 31 ++++ hyperram_model/hbc.v | 191 ++++++++++++++++++++++ hyperram_model/hbc_io.v | 37 +++++ hyperram_model/hbc_tb.v | 268 +++++++++++++++++++++++++++++++ hyperram_model/hbc_wrapper.v | 91 +++++++++++ hyperram_model/runhyperramsim.sh | 14 ++ src/ls2.py | 19 ++- 7 files changed, 647 insertions(+), 4 deletions(-) create mode 100644 hyperram_model/README.txt create mode 100644 hyperram_model/hbc.v create mode 100644 hyperram_model/hbc_io.v create mode 100644 hyperram_model/hbc_tb.v create mode 100644 hyperram_model/hbc_wrapper.v create mode 100755 hyperram_model/runhyperramsim.sh diff --git a/hyperram_model/README.txt b/hyperram_model/README.txt new file mode 100644 index 0000000..f2cf555 --- /dev/null +++ b/hyperram_model/README.txt @@ -0,0 +1,31 @@ +1) download the Cypress HyperRAM Model + http://www.cypress.com/verilog/s27kl0641-verilog +2) install icarus verilog +3) run ./runhyperramsim.sh + +Cypress HyperRAM Model files are +Copyright (C) 2015 Spansion, LLC. +(no explicit license found, but they are available publicly for download) + +hbc_*.v files from https://github.com/gtjennings1/HyperBUS are +Copyright 2017 Gnarly Grey LLC and have been released under this +license by Gnarly Grey: + +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: + +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/hyperram_model/hbc.v b/hyperram_model/hbc.v new file mode 100644 index 0000000..d33a501 --- /dev/null +++ b/hyperram_model/hbc.v @@ -0,0 +1,191 @@ +// Copyright 2017 Gnarly Grey LLC + +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: + +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +module hbc + ( + input i_clk, + input i_rstn, + + input i_cfg_access, + input i_mem_valid, + output o_mem_ready, + input [3:0] i_mem_wstrb, + input [31:0] i_mem_addr, + input [31:0] i_mem_wdata, + output [31:0] o_mem_rdata, + + output o_csn0, + output o_csn1, + output o_clk, + output o_clkn, + output [7:0] o_dq, + input [7:0] i_dq, + output o_dq_de, + output o_rwds, + input i_rwds, + output o_rwds_de, + output o_resetn + ); + + // fsm states + parameter IDLE = 0; + parameter CAs = 1; + parameter WR_LATENCY = 2; + parameter WRITE = 3; + parameter READ = 4; + parameter DONE = 5; + + // write latency + parameter WRITE_LATENCY = 6*2+10 - 1; + + reg [2:0] state; + reg [47:0] ca; + reg [31:0] wdata; + reg [3:0] wstrb; + integer counter; + + reg mem_ready; + reg [31:0] mem_rdata; + reg rwds_d; + wire rwds_valid; + + wire [7:0] ca_words[5:0]; + wire [7:0] wdata_words[3:0]; + wire [3:0] wstrb_words; + + // fsm + always @(posedge i_clk or negedge i_rstn) begin + if(!i_rstn) begin + ca <= 48'h0; + state <= IDLE; + mem_ready <= 1'b0; + mem_rdata <= 0; + counter <= 0; + end else begin + rwds_d <= i_rwds; + case (state) + IDLE : begin// wait for mem transaction + mem_ready <= 1'b0; + if(i_mem_valid && !mem_ready) begin + ca[47] <= ~(|i_mem_wstrb); + ca[46] <= i_cfg_access; + ca[45] <= (|i_mem_wstrb) & i_cfg_access; + ca[44:16] <= i_mem_addr[31:3]; + ca[15:3] <= 0; + ca[2:0] <= i_mem_addr[2:0]; + wdata <= i_mem_wdata; + wstrb <= i_mem_wstrb; + counter <= 5; + state <= CAs; + end + end + CAs: begin + if(counter) begin + counter <= counter - 1; + end else if(ca[47]) begin // read + counter <= 3; + state <= READ; + end else begin + if (ca[46]) begin // write to register + counter <= 1; + state <= WRITE; + end else begin // write to memory + counter <= WRITE_LATENCY; + state <= WR_LATENCY; + end + end + end + WR_LATENCY: begin + if(counter) begin + counter <= counter - 1; + end else begin + counter <= 3; + state <= WRITE; + end + end + WRITE: begin + if(counter) begin + counter <= counter - 1; + end else begin + state <= DONE; + end + end + READ : begin + if(rwds_valid) begin + case (counter) + 3: mem_rdata[15:8] <= i_dq; + 2: mem_rdata[7:0] <= i_dq; + 1: mem_rdata[31:24] <= i_dq; + 0: mem_rdata[23:16] <= i_dq; + endcase + if(counter) begin + counter <= counter - 1; + end else begin + state <= DONE; + end + end + end + DONE: begin + mem_ready <= 1'b1; + state <= IDLE; + end + endcase + end + end + + assign rwds_valid = (rwds_d | i_rwds); + assign ca_words[5] = ca[47:40]; + assign ca_words[4] = ca[39:32]; + assign ca_words[3] = ca[31:24]; + assign ca_words[2] = ca[23:16]; + assign ca_words[1] = ca[15:8]; + assign ca_words[0] = ca[7:0]; + assign wdata_words[3] = wdata[15:8]; + assign wdata_words[2] = wdata[7:0]; + assign wdata_words[1] = ca[46]?wdata[15:8]:wdata[31:24]; + assign wdata_words[0] = ca[46]?wdata[7:0]:wdata[23:16]; + assign wstrb_words = {wstrb[1], wstrb[0], wstrb[3], wstrb[2]}; + + reg bus_clk; + always @(negedge i_clk or negedge i_rstn) begin + if(!i_rstn) + bus_clk <= 0; + else + bus_clk <= o_csn0 ? 0 : ~bus_clk; + end + + assign o_csn0 = (state == IDLE || state == DONE); + assign o_csn1 = 1'b1; + assign o_clk = bus_clk; + assign o_clkn = ~o_clk; + assign o_resetn = i_rstn; + assign o_dq = (state == CAs)? ca_words[counter]: + (state == WRITE)? wdata_words[counter]:8'h0; + assign o_rwds = (state == WRITE)? ~wstrb_words[counter]:1'b0; + assign o_dq_de = (state == WRITE || state == CAs); + assign o_rwds_de = (state == WRITE) && (~ca[46]); + assign o_mem_ready = mem_ready; + assign o_mem_rdata = mem_rdata; + +endmodule + + diff --git a/hyperram_model/hbc_io.v b/hyperram_model/hbc_io.v new file mode 100644 index 0000000..b33e5a1 --- /dev/null +++ b/hyperram_model/hbc_io.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:56:04 08/10/2018 +// Design Name: +// Module Name: hbc_io +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module hbc_io( + input RWDS_o, + output RWDS_i, + input RWDS_de, + inout RWDS, + input [7:0] DQ_o, + output [7:0] DQ_i, + input DQ_de, + inout [7:0] DQ + ); + +assign DQ = DQ_de?DQ_o:8'hZZ; +assign RWDS = RWDS_de?RWDS_o:1'bZ; +assign RWDS_i = RWDS; +assign DQ_i = DQ; + +endmodule diff --git a/hyperram_model/hbc_tb.v b/hyperram_model/hbc_tb.v new file mode 100644 index 0000000..e7fcf71 --- /dev/null +++ b/hyperram_model/hbc_tb.v @@ -0,0 +1,268 @@ +// Copyright 2017 Gnarly Grey LLC + +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: + +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +`timescale 1ns/1ps + +module hbc_tb; + +// Inputs + reg i_clk; + reg i_rstn; + reg i_cfg_access; + reg i_mem_valid; + reg [3:0] i_mem_wstrb; + reg [31:0] i_mem_addr; + reg [31:0] i_mem_wdata; + + // Outputs + wire o_mem_ready; + wire [31:0] o_mem_rdata; + wire o_csn0; + wire o_csn1; + wire o_clk; + wire o_clkn; + wire o_resetn; + + // Bidirs + wire [7:0] io_dq; + wire io_rwds; + + reg [31:0] test_data [0:31]; + integer i, k; + integer uint8_addr = 0; + integer uint16_addr = 128; + integer uint32_addr = 256; + +hbc_wrapper hbc ( + .i_clk(i_clk), + .i_rstn(i_rstn), + .i_cfg_access(i_cfg_access), + .i_mem_valid(i_mem_valid), + .o_mem_ready(o_mem_ready), + .i_mem_wstrb(i_mem_wstrb), + .i_mem_addr(i_mem_addr), + .i_mem_wdata(i_mem_wdata), + .o_mem_rdata(o_mem_rdata), + .o_csn0(o_csn0), + .o_csn1(o_csn1), + .o_clk(o_clk), + .o_clkn(o_clkn), + .io_dq(io_dq), + .io_rwds(io_rwds), + .o_resetn(o_resetn) + ); + +s27kl0641 + #( + .TimingModel("S27KL0641DABHI000")) + hyperram ( + .DQ7(io_dq[7]), + .DQ6(io_dq[6]), + .DQ5(io_dq[5]), + .DQ4(io_dq[4]), + .DQ3(io_dq[3]), + .DQ2(io_dq[2]), + .DQ1(io_dq[1]), + .DQ0(io_dq[0]), + .RWDS(io_rwds), + .CSNeg(o_csn0), + .CK(o_clk), + .RESETNeg(o_resetn) + ); + + + initial begin + // Initialize Inputs + i_clk = 0; + i_rstn = 0; + i_cfg_access = 0; + i_mem_valid = 0; + i_mem_wstrb = 0; + i_mem_addr = 0; + i_mem_wdata = 0; + + + #100; + i_rstn = 1; + + $display("Waiting for device power-up..."); + #160e6; + $display("Reading the ID/CFG registers"); + + i_cfg_access = 1; + i_mem_valid = 1; + i_mem_wstrb = 0; + i_mem_addr = 0; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + $display("ID0: 0x%H", o_mem_rdata[15:0]); + #20; + i_mem_valid = 1; + i_mem_wstrb = 0; + i_mem_addr = 2; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + $display("ID1: 0x%H", o_mem_rdata[15:0]); + #20; + i_mem_valid = 1; + i_mem_wstrb = 0; + i_mem_addr = 2048; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + $display("CFG0: 0x%H", o_mem_rdata[15:0]); + #20; + i_mem_valid = 1; + i_mem_wstrb = 0; + i_mem_addr = 2049; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + $display("CFG1: 0x%H", o_mem_rdata[15:0]); + #20; + i_cfg_access = 0; + test_data[0] = 32'hDEADBEEF; + for(i = 1; i < 32; i = i + 1) begin + test_data[i] = {test_data[i - 1][27:0], test_data[i - 1][31:28]}; + end + #20; + $display("UINT8_t test"); + for(i = 0; i < 32; i = i + 1) begin + i_mem_wdata = test_data[i]; + i_mem_addr = uint8_addr + (i << 2); + for(k = 0; k < 4; k = k + 1) begin + i_mem_valid = 1; + i_mem_wstrb = (1 << k); + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + #20; + end + end + #20; + $display("expected\tread\t\tstatus"); + i_mem_wstrb = 0; + for(i = 0; i < 32; i = i + 1) begin + i_mem_addr = uint8_addr + (i << 2); + for(k = 0; k < 4; k = k + 1) begin + i_mem_valid = 1; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + if((o_mem_rdata & (255 << k*8)) == (test_data[i] & (255 << k*8))) begin + $display("0x%H\t0x%H\tOK", (test_data[i] & (255 << k*8)), (o_mem_rdata & (255 << k*8))); + end else begin + $display("0x%H\t0x%H\tFAIL", (test_data[i] & (255 << k*8)), (o_mem_rdata & (255 << k*8))); + end + #20; + end + end + #20; + $display("UINT16_t test"); + for(i = 0; i < 32; i = i + 1) begin + i_mem_wdata = test_data[i]; + i_mem_addr = uint16_addr + (i << 2); + for(k = 0; k < 2; k = k + 1) begin + i_mem_valid = 1; + i_mem_wstrb = (3 << (k*2)); + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + #20; + end + end + #20; + $display("expected\tread\t\tstatus"); + i_mem_wstrb = 0; + for(i = 0; i < 32; i = i + 1) begin + i_mem_addr = uint8_addr + (i << 2); + for(k = 0; k < 2; k = k + 1) begin + i_mem_valid = 1; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + if((o_mem_rdata & (16'hFFFF << k*16)) == (test_data[i] & (16'hFFFF << k*16))) begin + $display("0x%H\t0x%H\tOK", (test_data[i] & (16'hFFFF << k*16)), (o_mem_rdata & (16'hFFFF << k*16))); + end else begin + $display("0x%H\t0x%H\tFAIL", (test_data[i] & (16'hFFFF << k*16)), (o_mem_rdata & (16'hFFFF << k*16))); + end + #20; + end + end + #20; + $display("UINT32_t test"); + for(i = 0; i < 32; i = i + 1) begin + i_mem_wdata = test_data[i]; + i_mem_addr = uint32_addr + (i << 2); + i_mem_valid = 1; + i_mem_wstrb = 15; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + #20; + end + #20; + $display("expected\tread\t\tstatus"); + i_mem_wstrb = 0; + for(i = 0; i < 32; i = i + 1) begin + i_mem_addr = uint8_addr + (i << 2); + i_mem_valid = 1; + #10; + i_mem_valid = 0; + wait(o_mem_ready == 1); + if(o_mem_rdata == test_data[i]) begin + $display("0x%H\t0x%H\tOK", (test_data[i]), (o_mem_rdata)); + end else begin + $display("0x%H\t0x%H\tFAIL", (test_data[i]), (o_mem_rdata)); + end + #20; + end + #20; + $stop; + end + + always @(*) begin + i_clk <= #5 ~i_clk; + end + + initial + begin + $dumpfile("hypersim.fst"); + $dumpvars(0, i_clk); + $dumpvars(0, i_rstn); + $dumpvars(0, o_clk); + $dumpvars(0, o_resetn); + $dumpvars(0, o_csn0); + $dumpvars(0, o_csn1); + $dumpvars(0, io_rwds); + $dumpvars(0, io_dq); + $dumpvars(0, i_cfg_access); + $dumpvars(0, i_mem_valid); + $dumpvars(0, o_mem_ready); + $dumpvars(0, i_mem_wstrb); + $dumpvars(0, i_mem_addr); + $dumpvars(0, i_mem_wdata); + $dumpvars(0, o_mem_rdata); + end + +endmodule diff --git a/hyperram_model/hbc_wrapper.v b/hyperram_model/hbc_wrapper.v new file mode 100644 index 0000000..e87714c --- /dev/null +++ b/hyperram_model/hbc_wrapper.v @@ -0,0 +1,91 @@ +// Copyright 2017 Gnarly Grey LLC + +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: + +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +module hbc_wrapper + ( + input i_clk, + input i_rstn, + + input i_cfg_access, + input i_mem_valid, + output o_mem_ready, + input [3:0] i_mem_wstrb, + input [31:0] i_mem_addr, + input [31:0] i_mem_wdata, + output [31:0] o_mem_rdata, + + output o_csn0, + output o_csn1, + output o_clk, + output o_clkn, + inout [7:0] io_dq, + inout io_rwds, + output o_resetn + ); + + +wire [7:0] dq_i; +wire [7:0] dq_o; +wire dq_de; +wire rwds_i; +wire rwds_de; +wire rwds_o; + +hbc u_hbc + ( + .i_clk(i_clk), + .i_rstn(i_rstn), + + .i_cfg_access(i_cfg_access), + .i_mem_valid(i_mem_valid), + .o_mem_ready(o_mem_ready), + .i_mem_wstrb(i_mem_wstrb), + .i_mem_addr(i_mem_addr), + .i_mem_wdata(i_mem_wdata), + .o_mem_rdata(o_mem_rdata), + + .o_csn0(o_csn0), + .o_csn1(o_csn1), + .o_clk(o_clk), + .o_clkn(o_clkn), + .o_dq(dq_o), + .i_dq(dq_i), + .o_dq_de(dq_de), + .o_rwds(rwds_o), + .i_rwds(rwds_i), + .o_rwds_de(rwds_de), + .o_resetn(o_resetn) + ); + +hbc_io u_hbc_io + ( + .RWDS_i(rwds_i), + .RWDS_de(rwds_de), + .RWDS_o(rwds_o), + .DQ_de(dq_de), + .DQ_i(dq_i), + .DQ_o(dq_o), + .RWDS(io_rwds), + .DQ(io_dq) + ); + +endmodule \ No newline at end of file diff --git a/hyperram_model/runhyperramsim.sh b/hyperram_model/runhyperramsim.sh new file mode 100755 index 0000000..43e4eb6 --- /dev/null +++ b/hyperram_model/runhyperramsim.sh @@ -0,0 +1,14 @@ +#!/bin/bash +# https://ftp.libre-soc.org/Infineon-Verilog_Model_for_HyperBus_interface-SimulationModels-v03_00-EN.zip +set -e + +LIB_DIR=./s27kl0641/model + +# string together the icarus verilog files and start runnin +iverilog -I${LIB_DIR} -Wall -g2012 -s hbc_tb -o hypersim \ + hbc_tb.v \ + hbc_wrapper.v \ + hbc_io.v \ + hbc.v \ + ${LIB_DIR}/s27kl0641.v +vvp -n hypersim -fst-speed diff --git a/src/ls2.py b/src/ls2.py index 22cc7e3..1968aa7 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -45,6 +45,7 @@ from gram.frontend.wishbone import gramWishbone # Board (and simulation) platforms from nmigen_boards.versa_ecp5 import VersaECP5Platform +from nmigen_boards.versa_ecp5 import VersaECP5Platform85 # custom board from nmigen_boards.ulx3s import ULX3S_85F_Platform from nmigen_boards.arty_a7 import ArtyA7_100Platform from nmigen_boards.test.blinky import Blinky @@ -269,7 +270,10 @@ class DDR3SoC(SoC, Elaboratable): firmware = "firmware/main.bin" # set up clock request generator - self.crg = ECPIX5CRG(clk_freq) + if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']: + self.crg = ECPIX5CRG(clk_freq) + if fpga in ['arty_a7']: + self.crg = ArtyCRG(clk_freq) # set up CPU, with 64-to-32-bit downconverters if add_cpu: @@ -420,7 +424,7 @@ class DDR3SoC(SoC, Elaboratable): comb = m.d.comb # add the peripherals and clock-reset-generator - if platform is not None: + if platform is not None and hasattr(self, "crg"): m.submodules.sysclk = self.crg if hasattr(self, "bootmem"): @@ -549,6 +553,7 @@ if __name__ == "__main__": if len(sys.argv) >= 2: fpga = sys.argv[1] platform_kls = {'versa_ecp5': VersaECP5Platform, + 'versa_ecp5_85': VersaECP5Platform85, 'ulx3s': ULX3S_85F_Platform, 'arty_a7': ArtyA7_100Platform, 'isim': IcarusVersaPlatform, @@ -556,12 +561,14 @@ if __name__ == "__main__": }[fpga] toolchain = {'arty_a7': "yosys_nextpnr", 'versa_ecp5': 'Trellis', + 'versa_ecp5_85': 'Trellis', 'isim': 'Trellis', 'ulx3s': 'Trellis', 'sim': None, }.get(fpga, None) dram_cls = {'arty_a7': None, 'versa_ecp5': MT41K64M16, + 'versa_ecp5_85': MT41K64M16, #'versa_ecp5': MT41K256M16, 'ulx3s': None, 'sim': MT41K256M16, @@ -578,6 +585,10 @@ if __name__ == "__main__": clk_freq = 100e6 if fpga == 'versa_ecp5': clk_freq = 50e6 # crank right down to test hyperram + if fpga == 'versa_ecp5_85': + clk_freq = 55e6 + if fpga == 'arty_a7': + clk_freq = 25e6 # select a firmware file firmware = None @@ -595,7 +606,7 @@ if __name__ == "__main__": # get DDR resource pins, disable if clock frequency is below 50 mhz for now ddr_pins = None if (clk_freq > 50e6 and platform is not None and - fpga in ['versa_ecp5', 'arty_a7', 'isim']): + fpga in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']): ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, xdr={"rst": 4, "clk":4, "a":4, @@ -619,7 +630,7 @@ if __name__ == "__main__": # Get HyperRAM pins hyperram_pins = None - if platform is not None and fpga in ['versa_ecp5']: + if platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85']: hyperram_ios = HyperRAMResource(0, cs_n="B13", dq="E14 C10 B10 E12 D12 A9 D11 D14", rwds="C14", rst_n="E13", ck_p="D13", -- 2.30.2