From 11e0dccbd5524dca935a4910d962055cc4ff199c Mon Sep 17 00:00:00 2001 From: Jordi Vaquero Date: Wed, 22 Jul 2020 13:20:46 +0200 Subject: [PATCH] arch-arm: Add System register trap check for EL1 This change adds and refactors the register trap checks for EL1 in the same function, unifying the registry trapping Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31694 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/insts/misc64.cc | 35 +++++++++++++++++++++++++++++++ src/arch/arm/isa/insts/data64.isa | 8 ------- src/arch/arm/miscregs.cc | 17 --------------- src/arch/arm/miscregs_types.hh | 1 + 4 files changed, 36 insertions(+), 25 deletions(-) diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 51e602863..49cc6b0f8 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -114,9 +114,26 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, uint32_t &immediate) const { const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); + const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); + const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); + const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); bool trap_to_sup = false; switch (misc_reg) { + case MISCREG_DAIF: + trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0; + trap_to_sup = trap_to_sup || + (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma); + break; + case MISCREG_DC_ZVA_Xt: + // In syscall-emulation mode, this test is skipped and DCZVA is always + // allowed at EL0 + trap_to_sup = el == EL0 && !sctlr.dze && FullSystem; + break; + case MISCREG_DC_CIVAC_Xt: + case MISCREG_DC_CVAC_Xt: + trap_to_sup = el == EL0 && !sctlr.uci; + break; case MISCREG_FPCR: case MISCREG_FPSR: case MISCREG_FPEXC32_EL2: @@ -127,6 +144,24 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, immediate = 0x1E00000; } break; + case MISCREG_DC_CVAU_Xt: + trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) && + el == EL1; + break; + case MISCREG_CTR_EL0: + trap_to_sup = el == EL0 && !sctlr.uct && + (!hcr.tge || (!scr.ns && !scr.eel2)); + break; + case MISCREG_MDCCSR_EL0: + { + DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1); + trap_to_sup = el == EL0 && mdscr.tdcc && + (hcr.tge == 0x0 || ( scr.ns == 0x0)); + } + break; + case MISCREG_ZCR_EL1: + trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0); + break; // Generic Timer case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: trap_to_sup = el == EL0 && diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 3c1e94153..1b099bf91 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -312,14 +312,6 @@ let {{ msrMrs64EnabledCheckCode = ''' // Check for read/write access right if (!can%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr, xc->tcBase())) { - if (flat_idx == MISCREG_DAIF || - flat_idx == MISCREG_DC_ZVA_Xt || - flat_idx == MISCREG_DC_CVAC_Xt || - flat_idx == MISCREG_DC_CIVAC_Xt - ) - return std::make_shared( - machInst, 0, EC_TRAPPED_MSR_MRS_64, - mnemonic); return std::make_shared(machInst, false, mnemonic); } diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index cc451c6c1..525fbcdde 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1415,23 +1415,6 @@ canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0)) return false; ExceptionLevel el = currEL(cpsr); - if (reg == MISCREG_DAIF) { - SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); - if (el == EL0 && !sctlr.uma) - return false; - } - if (FullSystem && reg == MISCREG_DC_ZVA_Xt) { - // In syscall-emulation mode, this test is skipped and DCZVA is always - // allowed at EL0 - SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); - if (el == EL0 && !sctlr.dze) - return false; - } - if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { - SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); - if (el == EL0 && !sctlr.uci) - return false; - } bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; bool el2_host = EL2Enabled(tc) && hcr.e2h; diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh index d3787ffae..3578f58c5 100644 --- a/src/arch/arm/miscregs_types.hh +++ b/src/arch/arm/miscregs_types.hh @@ -730,6 +730,7 @@ namespace ArmISA Bitfield<14> hde; Bitfield<13> res0_; Bitfield<12> udccdis; + Bitfield<12> tdcc; Bitfield<11, 7> res0_2; Bitfield<6> err; Bitfield<5, 2> moe; -- 2.30.2