From 11ef82c72623aa8649d80b3efbb629f73ad039cb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 25 Aug 2016 21:36:09 -0700 Subject: [PATCH] Allow reads from tdrdata registers --- riscv/processor.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 0a7912b..c3c66b7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -482,6 +482,9 @@ reg_t processor_t::get_csr(int which) case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TDRSELECT: return 0; + case CSR_TDRDATA1: return 0; + case CSR_TDRDATA2: return 0; + case CSR_TDRDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; -- 2.30.2