From 11f43caaeca166c96ae49dbd506b6f58dd4a13fb Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 27 Nov 2019 17:24:23 +0000 Subject: [PATCH] aco: fix i2i64 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler') Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann --- src/amd/compiler/aco_instruction_selection.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bcccd0435f1..cb33814f17f 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2033,8 +2033,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_i2i64: { Temp src = get_alu_src(ctx, instr->src[0]); - if (instr->src[0].src.ssa->bit_size == 32) { - bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u)); + if (src.regClass() == s1) { + Temp high = bld.sopc(aco_opcode::s_ashr_i32, bld.def(s1, scc), src, Operand(31u)); + bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high); + } else if (src.regClass() == v1) { + Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src); + bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high); } else { fprintf(stderr, "Unimplemented NIR instr bit size: "); nir_print_instr(&instr->instr, stderr); -- 2.30.2