From 11fd2268e511b17e3cc228b723dc4af13f067838 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:27:53 +0530 Subject: [PATCH] arch-power: Add hardware features This adds definitions for the hardware feature bits that are currently available from the AT_HWCAP and AT_HWCAP2 auxv entries for the Power architecture. These are being defined for future use. Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51 Signed-off-by: Sandipan Das --- src/arch/power/process.hh | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh index bd249a34d..337d2df14 100644 --- a/src/arch/power/process.hh +++ b/src/arch/power/process.hh @@ -49,5 +49,44 @@ class PowerProcess : public Process void argsInit(int pageSize); }; +enum PowerHWCAPFeature { + PPC_FEATURE_32 = ULL(1) << 31, // Always set for powerpc64 + PPC_FEATURE_64 = ULL(1) << 30, // Always set for powerpc64 + PPC_FEATURE_HAS_ALTIVEC = ULL(1) << 28, + PPC_FEATURE_HAS_FPU = ULL(1) << 27, + PPC_FEATURE_HAS_MMU = ULL(1) << 26, + PPC_FEATURE_UNIFIED_CACHE = ULL(1) << 24, + PPC_FEATURE_NO_TB = ULL(1) << 20, // 601/403gx have no timebase + PPC_FEATURE_POWER4 = ULL(1) << 19, // POWER4 ISA 2.00 + PPC_FEATURE_POWER5 = ULL(1) << 18, // POWER5 ISA 2.02 + PPC_FEATURE_POWER5_PLUS = ULL(1) << 17, // POWER5+ ISA 2.03 + PPC_FEATURE_CELL_BE = ULL(1) << 16, // CELL Broadband Engine + PPC_FEATURE_BOOKE = ULL(1) << 15, // ISA Category Embedded + PPC_FEATURE_SMT = ULL(1) << 14, // Simultaneous Multi-Threading + PPC_FEATURE_ICACHE_SNOOP = ULL(1) << 13, + PPC_FEATURE_ARCH_2_05 = ULL(1) << 12, // ISA 2.05 + PPC_FEATURE_PA6T = ULL(1) << 11, // PA Semi 6T Core + PPC_FEATURE_HAS_DFP = ULL(1) << 10, // Decimal FP Unit + PPC_FEATURE_POWER6_EXT = ULL(1) << 9, // P6 + mffgpr/mftgpr + PPC_FEATURE_ARCH_2_06 = ULL(1) << 8, // ISA 2.06 + PPC_FEATURE_HAS_VSX = ULL(1) << 7, // P7 Vector Extension + PPC_FEATURE_PSERIES_PERFMON_COMPAT = ULL(1) << 6, + PPC_FEATURE_TRUE_LE = ULL(1) << 1, + PPC_FEATURE_PPC_LE = ULL(1) << 0 +}; + +enum PowerHWCAP2Feature { + PPC_FEATURE2_ARCH_2_07 = ULL(1) << 31, // ISA 2.07 + PPC_FEATURE2_HAS_HTM = ULL(1) << 30, // Hardware Transactional Memory + PPC_FEATURE2_HAS_DSCR = ULL(1) << 29, // Data Stream Control Register + PPC_FEATURE2_HAS_EBB = ULL(1) << 28, // Event Base Branching + PPC_FEATURE2_HAS_ISEL = ULL(1) << 27, // Integer Select + PPC_FEATURE2_HAS_TAR = ULL(1) << 26, // Target Address Register + PPC_FEATURE2_HAS_VCRYPTO = ULL(1) << 25, // Vector AES category + PPC_FEATURE2_HTM_NOSC = ULL(1) << 24, + PPC_FEATURE2_ARCH_3_00 = ULL(1) << 23, // ISA 3.0 + PPC_FEATURE2_HAS_IEEE128 = ULL(1) << 22, // VSX IEEE Binary Float 128-bit +}; + #endif // __POWER_PROCESS_HH__ -- 2.30.2