From 120d9a72e51c1ab90bf9f5b4524c15960d5acd7d Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 2 Oct 2020 22:43:33 +0100 Subject: [PATCH] --- HDL_workflow.mdwn | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn index e660f797c..6530120ff 100644 --- a/HDL_workflow.mdwn +++ b/HDL_workflow.mdwn @@ -429,6 +429,16 @@ Note: an ongoing bug in maturin interferes with successful installation. This c See [[HDL_workflow/coriolis2]] page, for those people doing layout work. +## Chips4Makers JTAG + +As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written. + + git clone https://gitlab.com/Chips4Makers/c4m-jtag.git + +Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use. + +We added a DMI to JTAG bridge in LibreSOC which is directly connected to the core, to access registers and to be able to start and stop the core and change the PC. In combination with the JTAG Wishbone interface the test ASIC can have a bootloader uploaded directly into onboard SRAM and execution begun. + # Registering for git repository access After going through the onboarding process and having agreed to take -- 2.30.2