From 121377dc7338a6aa30abef173eb9603588235d35 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 27 Jul 2021 14:19:31 +0100 Subject: [PATCH] fix errors in detection of ffmadds (etc), enabling FFT twin-regs moed when it should not have been. affected fcoss/fsins/fcfids --- openpower/isatables/minor_59.csv | 6 +++--- src/openpower/decoder/power_decoder2.py | 14 ++++++++++---- src/openpower/sv/trans/svp64.py | 25 ++++++++++++++----------- 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index be66a56b..b014f319 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -17,6 +17,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmsubs,A, -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmadds,A, -----01101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffadds,A, ------01110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdmadds,A, -1000001100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsins,X, -1000101100,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcoss,X, +-----01111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fdmadds,A, +1000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fsins,X, +1000101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fcoss,X, diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index e0a49447..8bc3ec6b 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1024,10 +1024,16 @@ class PowerDecodeSubset(Elaboratable): # if bit-reverse mode requested bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE comb += self.use_svp64_ldst_dec.eq(bitrev) - # detect if SVP64 FFT mode enabled (really bad hack) - xo = Signal(1) # 1 bit from Major 59 XO field == 0b0XXXX - comb += xo.eq(self.dec.opcode_in[5]) - comb += self.use_svp64_fft.eq((major == 59) & (xo == 0b0)) + # detect if SVP64 FFT mode enabled (really bad hack), + # exclude fcfids and others + # XXX this is a REALLY bad hack, REALLY has to be done better. + # likely with a sub-decoder. + xo5 = Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX + comb += xo5.eq(self.dec.opcode_in[5]) + xo = Signal(5) # 5 bits from Minor 59 fcfids == 0b01110 + comb += xo.eq(self.dec.opcode_in[1:6]) + comb += self.use_svp64_fft.eq((major == 59) & (xo5 == 0b0) & + (xo != 0b01110)) # decoded/selected instruction flags comb += self.do_copy("data_len", self.op_get("ldst_len")) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 672de98f..deed174a 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -253,7 +253,7 @@ class SVP64Asm: insn = 59 << (31-5) # opcode 59, bits 0-5 insn |= fields[0] << (31-10) # RT , bits 6-10 insn |= fields[1] << (31-20) # RB , bits 16-20 - insn |= 0b1000001100 << (31-30) # XO , bits 21..30 + insn |= 0b1000001110 << (31-30) # XO , bits 21..30 if opcode == 'fsins.': insn |= 1 << (31-31) # Rc=1 , bit 31 log ("fsins", bin(insn)) @@ -268,10 +268,10 @@ class SVP64Asm: insn = 59 << (31-5) # opcode 59, bits 0-5 insn |= fields[0] << (31-10) # RT , bits 6-10 insn |= fields[1] << (31-20) # RB , bits 16-20 - insn |= 0b1000101100 << (31-30) # XO , bits 21..30 - if opcode == 'fsins.': + insn |= 0b1000101110 << (31-30) # XO , bits 21..30 + if opcode == 'fcoss.': insn |= 1 << (31-31) # Rc=1 , bit 31 - log ("fsins", bin(insn)) + log ("fcoss", bin(insn)) yield ".long 0x%x" % insn return @@ -888,7 +888,7 @@ class SVP64Asm: opcode |= int(v30b_newfields[1]) << (32-16) # FRA opcode |= int(v30b_newfields[2]) << (32-21) # FRB opcode |= int(v30b_newfields[3]) << (32-26) # FRC - opcode |= 0b01110 << (32-31) # bits 26-30 + opcode |= 0b01111 << (32-31) # bits 26-30 if rc: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode @@ -932,11 +932,11 @@ class SVP64Asm: elif v30b_op in ["fcoss", "fcoss."]: insn = 59 << (31-5) # opcode 59, bits 0-5 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10 - insn |= int(v30b_newfields[0]) << (31-20) # RB , bits 16-20 - insn |= 0b1000101100 << (31-30) # XO , bits 21..30 - if opcode == 'fsins.': + insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20 + insn |= 0b1000101110 << (31-30) # XO , bits 21..30 + if opcode == 'fcoss.': insn |= 1 << (31-31) # Rc=1 , bit 31 - log ("fsins", bin(insn)) + log ("fcoss", bin(insn)) yield ".long 0x%x" % insn else: @@ -1101,9 +1101,12 @@ if __name__ == '__main__': 'svshape 8, 1, 1, 1, 1', ] lst = [ - 'sv.lfsbr 4.v, 11(8.v), 15', + #'sv.lfsbr 4.v, 11(8.v), 15', #'sv.lwzbr 4.v, 11(8.v), 15', - 'sv.svstep. 2.v, 4, 0', + #'sv.svstep. 2.v, 4, 0', + #'sv.fcfids. 48.v, 64.v', + 'sv.fcoss. 80.v, 0.v', + 'sv.fcoss. 20.v, 0.v', ] isa = SVP64Asm(lst, macros=macros) print ("list", list(isa)) -- 2.30.2