From 12172071b5f5cb7f475a20ead8a65eb12fa94737 Mon Sep 17 00:00:00 2001 From: Andre Maasikas Date: Mon, 26 Apr 2010 13:18:04 +0300 Subject: [PATCH] r600: enable VERT_RESULT_PSIZ - makes point size & attenuation work doc additions: shader export ARRAY_BASE for EXPORT_POS: 60 is position, 61 is misc vec(VS_OUT_MISC_VEC - used here), 62, 63 are clip distance vectors(VS_OUT_CCDIST#) sorry for formating - there seem to be so many different styles in r600 --- src/mesa/drivers/dri/r600/r700_assembler.c | 21 +++++++++++++++++++-- src/mesa/drivers/dri/r600/r700_vertprog.c | 10 ++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 834bcc63e31..0677c54bea1 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -6511,13 +6511,30 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode, { return GL_FALSE; } + export_starting_index++; + export_count--; + } + unBit = 1 << VERT_RESULT_PSIZ; + if(OutputsWritten & unBit) + { + if( GL_FALSE == Process_Export(pR700AsmCode, + SQ_EXPORT_POS, + export_starting_index, + 1, + pR700AsmCode->ucVP_OutputMap[VERT_RESULT_PSIZ], + GL_FALSE) ) + { + return GL_FALSE; + } export_count--; + } + + pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; - pR700AsmCode->cf_last_export_ptr->m_Word1.f.cf_inst = SQ_CF_INST_EXPORT_DONE; - } pR700AsmCode->number_of_exports = export_count; + export_starting_index = 0; unBit = 1 << VERT_RESULT_COL0; if(OutputsWritten & unBit) diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 05c65164d60..14dd2a5482c 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -628,6 +628,16 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) R600_STATECHANGE(context, spi); + if(vp->mesa_program->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ)) { + R600_STATECHANGE(context, cl); + SETbit(r700->PA_CL_VS_OUT_CNTL.u32All, USE_VTX_POINT_SIZE_bit); + SETbit(r700->PA_CL_VS_OUT_CNTL.u32All, VS_OUT_MISC_VEC_ENA_bit); + } else if (r700->PA_CL_VS_OUT_CNTL.u32All != 0) { + R600_STATECHANGE(context, cl); + CLEARbit(r700->PA_CL_VS_OUT_CNTL.u32All, USE_VTX_POINT_SIZE_bit); + CLEARbit(r700->PA_CL_VS_OUT_CNTL.u32All, VS_OUT_MISC_VEC_ENA_bit); + } + SETfield(r700->SPI_VS_OUT_CONFIG.u32All, vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0, VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask); -- 2.30.2