From 125d71dba41f02cf38b79a702dc25efeb3d2cf79 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Jul 2020 14:24:30 +0100
Subject: [PATCH] add PC (CIA) to PowerDecode2 "state" for passing into input
 records see https://bugs.libre-soc.org/show_bug.cgi?id=435

---
 src/soc/decoder/decode2execute1.py | 8 ++++++--
 src/soc/decoder/power_decoder2.py  | 9 +++++++--
 src/soc/simple/issuer.py           | 7 ++++++-
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index cf1c633c..410cb7ec 100644
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -29,10 +29,15 @@ class Decode2ToOperand(RecordObject):
 
         RecordObject.__init__(self, name=name)
 
+        # current "state" (TODO: this in its own Record)
+        self.msr = Signal(64, reset_less=True)
+        self.cia = Signal(64, reset_less=True)
+
+        # instruction, type and decoded information
+        self.insn = Signal(32, reset_less=True) # original instruction
         self.insn_type = Signal(MicrOp, reset_less=True)
         self.fn_unit = Signal(Function, reset_less=True)
         self.imm_data = Data(64, name="imm")
-
         self.lk = Signal(reset_less=True)
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
@@ -45,7 +50,6 @@ class Decode2ToOperand(RecordObject):
         self.invert_out = Signal(reset_less=True)
         self.is_32bit = Signal(reset_less=True)
         self.is_signed = Signal(reset_less=True)
-        self.insn = Signal(32, reset_less=True)
         self.data_len = Signal(4, reset_less=True) # bytes
         self.byte_reverse  = Signal(reset_less=True)
         self.sign_extend  = Signal(reset_less=True)# do we need this?
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 323e49a7..6ab61d2b 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -561,8 +561,9 @@ class PowerDecode2(Elaboratable):
         self.e = Decode2ToExecute1Type()
         self.valid = Signal() # sync signal
 
-        # state information needed by the Decoder
+        # state information needed by the Decoder (TODO: this as a Record)
         self.msr = Signal(64, reset_less=True) # copy of MSR
+        self.cia = Signal(64, reset_less=True) # copy of Program Counter
 
     def ports(self):
         return self.dec.ports() + self.e.ports()
@@ -570,7 +571,7 @@ class PowerDecode2(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        e, op, do, msr = self.e, self.dec.op, self.e.do, self.msr
+        e, op, do, msr, cia = self.e, self.dec.op, self.e.do, self.msr, self.cia
 
         # set up submodule decoders
         m.submodules.dec = self.dec
@@ -603,6 +604,10 @@ class PowerDecode2(Elaboratable):
         comb += dec_cr_out.sel_in.eq(op.cr_out)
         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 
+        # copy "state" over
+        comb += do.msr.eq(self.msr)
+        comb += do.cia.eq(self.cia)
+
         # set up instruction, pick fn unit
         comb += do.insn_type.eq(op.internal_op) # no op: defaults to OP_ILLEGAL
         comb += do.fn_unit.eq(op.function_unit)
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 59b463b0..10f45586 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -108,6 +108,7 @@ class TestIssuer(Elaboratable):
 
         insn_type = core.pdecode2.e.do.insn_type
         insn_msr = core.pdecode2.msr
+        insn_cia = core.pdecode2.cia
 
         # only run if not in halted state
         with m.If(~core.core_terminated_o):
@@ -156,12 +157,15 @@ class TestIssuer(Elaboratable):
                         comb += core_opcode_i.eq(current_insn) # actual opcode
                         sync += ilatch.eq(current_insn) # latch current insn
 
-                        # read MSR
+                        # read MSR, latch it, and put it in decode "state"
                         comb += self.fast_r_msr.ren.eq(1<<FastRegs.MSR)
                         comb += msr.eq(self.fast_r_msr.data_o)
                         comb += insn_msr.eq(msr)
                         sync += cur_msr.eq(msr) # latch current MSR
 
+                        # also drop PC into decode "state"
+                        comb += insn_cia.eq(cur_pc)
+
                         m.next = "INSN_ACTIVE" # move to "wait completion" 
 
                 # instruction started: must wait till it finishes
@@ -173,6 +177,7 @@ class TestIssuer(Elaboratable):
                             comb += core_ivalid_i.eq(1) # instruction is valid
                         comb += core_opcode_i.eq(ilatch) # actual opcode
                         comb += insn_msr.eq(cur_msr)     # and MSR
+                        comb += insn_cia.eq(cur_pc)     # and PC
                         with m.If(self.fast_nia.wen):
                             sync += pc_changed.eq(1)
                         with m.If(~core_busy_o): # instruction done!
-- 
2.30.2