From 1275e2f150552c5b257368c7a00078c120cf2918 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 15 Apr 2019 16:48:47 +0200 Subject: [PATCH] build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set quiet property to avoid generating false warnings. --- litex/build/xilinx/vivado.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index b9750bba..81af2b0c 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -197,23 +197,23 @@ class XilinxVivadoToolchain: # The asynchronous input to a MultiReg is a false path platform.add_platform_command( "set_false_path -quiet " - "-to [get_nets -filter {{mr_ff == TRUE}}]" + "-to [get_nets -quiet -filter {{mr_ff == TRUE}}]" ) # The asychronous reset input to the AsyncResetSynchronizer is a false # path platform.add_platform_command( "set_false_path -quiet " - "-to [get_pins -filter {{REF_PIN_NAME == PRE}} " - "-of [get_cells -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" + "-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} " + "-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" ) # clock_period-2ns to resolve metastability on the wire between the # AsyncResetSynchronizer FFs platform.add_platform_command( "set_max_delay 2 -quiet " - "-from [get_pins -filter {{REF_PIN_NAME == Q}} " - "-of [get_cells -filter {{ars_ff1 == TRUE}}]] " - "-to [get_pins -filter {{REF_PIN_NAME == D}} " - "-of [get_cells -filter {{ars_ff2 == TRUE}}]]" + "-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} " + "-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] " + "-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} " + "-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]" ) def build(self, platform, fragment, build_dir="build", build_name="top", -- 2.30.2