From 1281a463d6c959f67741fc17ffe5d7ed4078c02b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 May 2015 17:42:00 +0200 Subject: [PATCH] litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data). - we can now pass a phy to LiteScopeWishboneBridge - LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge - UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug. --- .../liteeth/example_designs/targets/base.py | 4 +- .../com/liteeth/example_designs/test/make.py | 4 +- .../litepcie/example_designs/targets/dma.py | 4 +- .../com/litepcie/example_designs/test/make.py | 4 +- .../litesata/example_designs/targets/bist.py | 4 +- .../mem/litesata/example_designs/test/bist.py | 4 +- .../mem/litesata/example_designs/test/make.py | 4 +- .../bridge/{uart2wb.py => wishbone.py} | 87 +++++-------------- .../example_designs/targets/simple.py | 4 +- .../litescope/example_designs/test/make.py | 4 +- misoclib/tools/litescope/host/driver/uart.py | 10 +-- 11 files changed, 39 insertions(+), 94 deletions(-) rename misoclib/tools/litescope/bridge/{uart2wb.py => wishbone.py} (61%) diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 83b47ff1..5d501df1 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -4,7 +4,7 @@ from migen.genlib.io import CRG from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB +from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm @@ -30,7 +30,7 @@ class BaseSoC(SoC, AutoCSR): with_identifier=True, with_timer=False ) - self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) diff --git a/misoclib/com/liteeth/example_designs/test/make.py b/misoclib/com/liteeth/example_designs/test/make.py index aa3c5cce..2922b9a1 100755 --- a/misoclib/com/liteeth/example_designs/test/make.py +++ b/misoclib/com/liteeth/example_designs/test/make.py @@ -19,9 +19,9 @@ def _get_args(): if __name__ == "__main__": args = _get_args() if args.bridge == "uart": - from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver + from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver port = args.port if not args.port.isdigit() else int(args.port) - wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) elif args.bridge == "etherbone": from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py index 34783672..240f5cef 100644 --- a/misoclib/com/litepcie/example_designs/targets/dma.py +++ b/misoclib/com/litepcie/example_designs/targets/dma.py @@ -6,7 +6,7 @@ from migen.genlib.misc import timeline from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB +from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY from misoclib.com.litepcie.core import Endpoint @@ -82,7 +82,7 @@ class PCIeDMASoC(SoC, AutoCSR): self.dma.source.connect(self.dma.sink) if with_uart_bridge: - self.submodules.uart_bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200) + self.submodules.uart_bridge = LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200) self.add_wb_master(self.uart_bridge.wishbone) # IRQs diff --git a/misoclib/com/litepcie/example_designs/test/make.py b/misoclib/com/litepcie/example_designs/test/make.py index f29f45a0..c1020000 100755 --- a/misoclib/com/litepcie/example_designs/test/make.py +++ b/misoclib/com/litepcie/example_designs/test/make.py @@ -21,9 +21,9 @@ def _get_args(): if __name__ == "__main__": args = _get_args() if args.bridge == "uart": - from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver + from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver port = args.port if not args.port.isdigit() else int(args.port) - wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) elif args.bridge == "etherbone": from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index e52e8547..3238bd8f 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -6,7 +6,7 @@ from migen.bank.description import * from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB +from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm @@ -99,7 +99,7 @@ class BISTSoC(SoC, AutoCSR): with_identifier=True, with_timer=False ) - self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = _CRG(platform) diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py index 2b27206c..e610ebf4 100644 --- a/misoclib/mem/litesata/example_designs/test/bist.py +++ b/misoclib/mem/litesata/example_designs/test/bist.py @@ -2,7 +2,7 @@ import time import argparse import random as rand from collections import OrderedDict -from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver +from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver KB = 1024 MB = 1024*KB @@ -149,7 +149,7 @@ SATA BIST utility. if __name__ == "__main__": args = _get_args() - wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + wb = LiteScopeUART2WishboneDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False) wb.open() # # # identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist") diff --git a/misoclib/mem/litesata/example_designs/test/make.py b/misoclib/mem/litesata/example_designs/test/make.py index f7a9ec67..47278051 100755 --- a/misoclib/mem/litesata/example_designs/test/make.py +++ b/misoclib/mem/litesata/example_designs/test/make.py @@ -19,9 +19,9 @@ def _get_args(): if __name__ == "__main__": args = _get_args() if args.bridge == "uart": - from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver + from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver port = args.port if not args.port.isdigit() else int(args.port) - wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) elif args.bridge == "etherbone": from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/wishbone.py similarity index 61% rename from misoclib/tools/litescope/bridge/uart2wb.py rename to misoclib/tools/litescope/bridge/wishbone.py index 08e4ec03..4930f68a 100644 --- a/misoclib/tools/litescope/bridge/uart2wb.py +++ b/misoclib/tools/litescope/bridge/wishbone.py @@ -1,74 +1,22 @@ from misoclib.tools.litescope.common import * from migen.bus import wishbone from migen.genlib.misc import chooser -from migen.genlib.cdc import MultiReg -from migen.bank.description import * -from migen.bank.eventmanager import * from migen.genlib.record import Record from migen.flow.actor import Sink, Source from misoclib.com.uart.phy.serial import UARTPHYSerial - -class UARTPads: - def __init__(self): - self.rx = Signal() - self.tx = Signal() - - -class UARTMux(Module): - def __init__(self, pads): - self.sel = Signal(max=2) - self.shared_pads = UARTPads() - self.bridge_pads = UARTPads() - - # # # - - # Route rx pad: - # when sel==0, route it to shared rx and bridge rx - # when sel==1, route it only to bridge rx - self.comb += \ - If(self.sel == 0, - self.shared_pads.rx.eq(pads.rx), - self.bridge_pads.rx.eq(pads.rx) - ).Else( - self.bridge_pads.rx.eq(pads.rx) - ) - - # Route tx: - # when sel==0, route shared tx to pads tx - # when sel==1, route bridge tx to pads tx - self.comb += \ - If(self.sel == 0, - pads.tx.eq(self.shared_pads.tx) - ).Else( - pads.tx.eq(self.bridge_pads.tx) - ) - - -class LiteScopeUART2WB(Module, AutoCSR): +class LiteScopeWishboneBridge(Module): cmds = { "write": 0x01, "read": 0x02 } - def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False): + def __init__(self, phy, clk_freq): self.wishbone = wishbone.Interface() - if share_uart: - self._sel = CSRStorage() # # # - if share_uart: - mux = UARTMux(pads) - uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate) - self.submodules += mux, uart - self.shared_pads = mux.shared_pads - self.comb += mux.sel.eq(self._sel.storage) - else: - uart = UARTPHYSerial(pads, clk_freq, baudrate) - self.submodules += uart - byte_counter = Counter(3) word_counter = Counter(8) self.submodules += byte_counter, word_counter @@ -87,11 +35,11 @@ class LiteScopeUART2WB(Module, AutoCSR): tx_data_ce = Signal() self.sync += [ - If(cmd_ce, cmd.eq(uart.source.data)), - If(length_ce, length.eq(uart.source.data)), - If(address_ce, address.eq(Cat(uart.source.data, address[0:24]))), + If(cmd_ce, cmd.eq(phy.source.data)), + If(length_ce, length.eq(phy.source.data)), + If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))), If(rx_data_ce, - data.eq(Cat(uart.source.data, data[0:24])) + data.eq(Cat(phy.source.data, data[0:24])) ).Elif(tx_data_ce, data.eq(self.wishbone.dat_r) ) @@ -106,10 +54,10 @@ class LiteScopeUART2WB(Module, AutoCSR): ] fsm.act("IDLE", timeout.reset.eq(1), - If(uart.source.stb, + If(phy.source.stb, cmd_ce.eq(1), - If((uart.source.data == self.cmds["write"]) | - (uart.source.data == self.cmds["read"]), + If((phy.source.data == self.cmds["write"]) | + (phy.source.data == self.cmds["read"]), NextState("RECEIVE_LENGTH") ), byte_counter.reset.eq(1), @@ -117,13 +65,13 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ) fsm.act("RECEIVE_LENGTH", - If(uart.source.stb, + If(phy.source.stb, length_ce.eq(1), NextState("RECEIVE_ADDRESS") ) ) fsm.act("RECEIVE_ADDRESS", - If(uart.source.stb, + If(phy.source.stb, address_ce.eq(1), byte_counter.ce.eq(1), If(byte_counter.value == 3, @@ -137,7 +85,7 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ) fsm.act("RECEIVE_DATA", - If(uart.source.stb, + If(phy.source.stb, rx_data_ce.eq(1), byte_counter.ce.eq(1), If(byte_counter.value == 3, @@ -174,10 +122,10 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ) self.comb += \ - chooser(data, byte_counter.value, uart.sink.data, n=4, reverse=True) + chooser(data, byte_counter.value, phy.sink.data, n=4, reverse=True) fsm.act("SEND_DATA", - uart.sink.stb.eq(1), - If(uart.sink.ack, + phy.sink.stb.eq(1), + If(phy.sink.ack, byte_counter.ce.eq(1), If(byte_counter.value == 3, word_counter.ce.eq(1), @@ -190,3 +138,8 @@ class LiteScopeUART2WB(Module, AutoCSR): ) ) ) + +class LiteScopeUART2Wishbone(LiteScopeWishboneBridge): + def __init__(self, pads, clk_freq, baudrate=115200): + self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate) + LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq) diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index dfc0f348..f8ebf756 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -3,7 +3,7 @@ from migen.genlib.io import CRG from misoclib.soc import SoC from misoclib.tools.litescope.common import * -from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB +from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone from misoclib.tools.litescope.frontend.io import LiteScopeIO from misoclib.tools.litescope.frontend.la import LiteScopeLA from misoclib.tools.litescope.core.port import LiteScopeTerm @@ -25,7 +25,7 @@ class LiteScopeSoC(SoC, AutoCSR): with_identifier=True, with_timer=False ) - self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) diff --git a/misoclib/tools/litescope/example_designs/test/make.py b/misoclib/tools/litescope/example_designs/test/make.py index f7a9ec67..47278051 100755 --- a/misoclib/tools/litescope/example_designs/test/make.py +++ b/misoclib/tools/litescope/example_designs/test/make.py @@ -19,9 +19,9 @@ def _get_args(): if __name__ == "__main__": args = _get_args() if args.bridge == "uart": - from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver + from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver port = args.port if not args.port.isdigit() else int(args.port) - wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) + wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False) elif args.bridge == "etherbone": from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False) diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py index b1e42ead..c4c90071 100644 --- a/misoclib/tools/litescope/host/driver/uart.py +++ b/misoclib/tools/litescope/host/driver/uart.py @@ -7,7 +7,7 @@ def write_b(uart, data): uart.write(pack('B', data)) -class LiteScopeUARTDriver: +class LiteScopeUART2WishboneDriver: cmds = { "write": 0x01, "read": 0x02 @@ -25,16 +25,8 @@ class LiteScopeUARTDriver: self.uart.close() self.uart.open() self.uart.flushInput() - try: - self.regs.uart2wb_sel.write(1) - except: - pass def close(self): - try: - self.regs.uart2wb_sel.write(0) - except: - pass self.uart.flushOutput() self.uart.close() -- 2.30.2