From 1315b4cb60e55c983ca2dac72b239cd9bc72bf9d Mon Sep 17 00:00:00 2001
From: Andrew Cagney <cagney@redhat.com>
Date: Fri, 24 Oct 1997 00:52:23 +0000
Subject: [PATCH] Address MSC compiler issues in d10v_sim.h

---
 sim/d10v/ChangeLog | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index bee6a0cfaaa..21f222ea90c 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,11 @@
+Fri Oct 24 10:26:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* d10v_sim.h: Include sim-types.h.
+	(uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef
+ 	using unsigned8 et.al. from sim-types.h.
+	(SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with
+ 	SIGNED64 macro.
+
 Wed Oct 22 14:43:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* interp.c (sim_write_phys): New function, write to physical
-- 
2.30.2