From 131b93797570728c4158cec388cd3354af104b64 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 17:38:04 +0000 Subject: [PATCH] set power type in fake pll vdd/vss --- experiments10_verilog/pll.py | 2 ++ experiments9/pll.py | 2 ++ 2 files changed, 4 insertions(+) diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py index 03a6ccc..07a89a9 100644 --- a/experiments10_verilog/pll.py +++ b/experiments10_verilog/pll.py @@ -237,6 +237,8 @@ def _load(): nets['div_out_test'].setDirection( Net.Direction.OUT ) nets['vco_test_ana'].setDirection( Net.Direction.OUT ) nets['out_v'].setDirection( Net.Direction.OUT ) + nets['vdd'].setType( Net.Type.POWER ) + nets['vss'].setType( Net.Type.GROUND ) # create series of stepped pins x = space*20 diff --git a/experiments9/pll.py b/experiments9/pll.py index 03a6ccc..07a89a9 100644 --- a/experiments9/pll.py +++ b/experiments9/pll.py @@ -237,6 +237,8 @@ def _load(): nets['div_out_test'].setDirection( Net.Direction.OUT ) nets['vco_test_ana'].setDirection( Net.Direction.OUT ) nets['out_v'].setDirection( Net.Direction.OUT ) + nets['vdd'].setType( Net.Type.POWER ) + nets['vss'].setType( Net.Type.GROUND ) # create series of stepped pins x = space*20 -- 2.30.2