From 135a4fea25a776fcce0c8f19a23df26fcb34140c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 11 Dec 2013 22:26:10 +0100 Subject: [PATCH] fhdl/verilog: fix representation of negative integers Give the explicit two's complement representation for the given bit width. This results in less readable code compared to using unary minus, but fixes a bug when trying to represent the most negative integer. --- migen/fhdl/verilog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index fc56f784..684812a5 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -27,7 +27,8 @@ def _printintbool(node): if node >= 0: return str(bits_for(node)) + "'d" + str(node), False else: - return "-" + str(bits_for(node)) + "'sd" + str(-node), True + nbits = bits_for(node) + return str(nbits) + "'sd" + str(2**nbits + node), True else: raise TypeError -- 2.30.2