From 13623a7d393cba33ea3b65399e031f21a28514a8 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Wed, 19 May 2021 13:33:48 +0300 Subject: [PATCH] Stop spamming the world whenever PowerDecoder is fired up --- src/openpower/decoder/power_svp64.py | 14 +++-- src/openpower/decoder/pseudo/pagereader.py | 21 +++++--- src/openpower/sv/trans/svp64.py | 62 +++++++++++++--------- 3 files changed, 61 insertions(+), 36 deletions(-) diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index 0fa44901..8c3aca32 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -29,7 +29,7 @@ def get_regtype(regname): return "FPR" -def decode_extra(rm, prefix=''): +def decode_extra(rm, prefix='', verbose=False): # first turn the svp64 rm into a "by name" dict, recording # which position in the RM EXTRA it goes into # also: record if the src or dest was a CR, for sanity-checking @@ -38,11 +38,13 @@ def decode_extra(rm, prefix=''): svp64_srcreg_byname = {} svp64_destreg_byname = {} for i in range(4): - print (rm) + if verbose: + print (rm) rfield = rm[prefix+str(i)] if not rfield or rfield == '0': continue - print ("EXTRA field", i, rfield) + if verbose: + print ("EXTRA field", i, rfield) rfield = rfield.split(";") # s:RA;d:CR1 etc. for r in rfield: rtype = r[0] @@ -73,6 +75,7 @@ class SVP64RM: """ self.instrs = {} self.svp64_instrs = {} + self.verbose = False pth = find_wiki_dir() for fname in os.listdir(pth): if fname.startswith("RM") or fname.startswith("LDSTRM"): @@ -120,7 +123,7 @@ class SVP64RM: # hmm, we need something more useful: a cross-association # of the in1/2/3 and CR in/out with the EXTRA0-3 fields - decode = decode_extra(entry, "EXTRA") + decode = decode_extra(entry, "EXTRA", self.verbose) dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode # now examine in1/2/3/out, create sv_in1/2/3/out @@ -129,7 +132,8 @@ class SVP64RM: extra_index = None if regfield == 'RA_OR_ZERO': regfield = 'RA' - print (asmcode, regfield, fname, svp64_dest, svp64_src) + if self.verbose: + print (asmcode, regfield, fname, svp64_dest, svp64_src) # find the reg in the SVP64 extra map if (fname in ['out', 'out2'] and regfield in svp64_dest): extra_index = svp64_dest[regfield] diff --git a/src/openpower/decoder/pseudo/pagereader.py b/src/openpower/decoder/pseudo/pagereader.py index d023ab57..d5cae081 100644 --- a/src/openpower/decoder/pseudo/pagereader.py +++ b/src/openpower/decoder/pseudo/pagereader.py @@ -58,7 +58,7 @@ def get_isa_dir(): fdir = os.path.split(fdir)[0] fdir = os.path.split(fdir)[0] fdir = os.path.split(fdir)[0] - print (fdir) + # print (fdir) return os.path.join(fdir, "openpower", "isa") @@ -68,8 +68,10 @@ class ISA: self.instr = OrderedDict() self.forms = {} self.page = {} + self.verbose = False for pth in os.listdir(os.path.join(get_isa_dir())): - print("examining", get_isa_dir(), pth) + if self.verbose: + print("examining", get_isa_dir(), pth) if "swp" in pth: continue if not pth.endswith(".mdwn"): @@ -93,7 +95,8 @@ class ISA: l = lines.pop(0).rstrip() # get first line rewrite.append(l) while lines: - print(l) + if self.verbose: + print(l) # look for HTML comment, if starting, skip line. # XXX this is braindead! it doesn't look for the end # so please put ending of comments on one line: @@ -113,7 +116,8 @@ class ISA: # whitespace expected l = lines.pop(0).strip() - print(repr(l)) + if self.verbose: + print(repr(l)) assert len(l) == 0, ("blank line not found %s" % l) rewrite.append(l) @@ -187,7 +191,8 @@ class ISA: l = lines.pop(0).rstrip() # get first line while lines: - print(l) + if self.verbose: + print(l) # look for HTML comment, if starting, skip line. # XXX this is braindead! it doesn't look for the end # so please put ending of comments on one line: @@ -209,7 +214,8 @@ class ISA: # whitespace expected l = lines.pop(0).strip() - print(repr(l)) + if self.verbose: + print(repr(l)) assert len(l) == 0, ("blank line not found %s" % l) # Form expected @@ -239,7 +245,8 @@ class ISA: # whitespace expected l = lines.pop(0).strip() - print(repr(l)) + if self.verbose: + print(repr(l)) assert len(l) == 0, ("blank line not found %s" % l) # get pseudocode diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index ef60dffa..e169329c 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -146,6 +146,7 @@ class SVP64Asm: def __init__(self, lst, bigendian=False): self.lst = lst self.trans = self.translate(lst) + self.verbose = False assert bigendian == False, "error, bigendian not supported yet" def __iter__(self): @@ -161,7 +162,8 @@ class SVP64Asm: # now find opcode fields fields = ''.join(ls[1:]).split(',') fields = list(map(str.strip, fields)) - print ("opcode, fields", ls, opcode, fields) + if self.verbose: + print ("opcode, fields", ls, opcode, fields) # sigh have to do setvl here manually for now... if opcode in ["setvl", "setvl."]: @@ -175,7 +177,8 @@ class SVP64Asm: insn |= 0b00000 << (31-30) # XO , bits 26..30 if opcode == 'setvl.': insn |= 1 << (31-31) # Rc=1 , bit 31 - print ("setvl", bin(insn)) + if self.verbose: + print ("setvl", bin(insn)) yield ".long 0x%x" % insn continue @@ -201,9 +204,10 @@ class SVP64Asm: (v30b_op, insn)) v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB" rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV - print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '') - print ("v3.0B regs", opcode, v30b_regs) - print (rm) + if self.verbose: + print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '') + print ("v3.0B regs", opcode, v30b_regs) + print (rm) # right. the first thing to do is identify the ordering of # the registers, by name. the EXTRA2/3 ordering is in @@ -221,7 +225,8 @@ class SVP64Asm: svp64_reg_byname.update(svp64_src) svp64_reg_byname.update(svp64_dest) - print ("EXTRA field index, by regname", svp64_reg_byname) + if self.verbose: + print ("EXTRA field index, by regname", svp64_reg_byname) # okaaay now we identify the field value (opcode N,N,N) with # the pseudo-code info (opcode RT, RA, RB) @@ -237,7 +242,8 @@ class SVP64Asm: extra = svp64_reg_byname.get(regname, None) rtype = get_regtype(regname) extras[extra] = (idx, field, regname, rtype, imm) - print (" ", extra, extras[extra]) + if self.verbose: + print (" ", extra, extras[extra]) # great! got the extra fields in their associated positions: # also we know the register type. now to create the EXTRA encodings @@ -257,8 +263,9 @@ class SVP64Asm: immed, field = field[:-1].split("(") field, regmode = decode_reg(field) - print (" ", extra_idx, rname, rtype, - regmode, iname, field, end=" ") + if self.verbose: + print (" ", extra_idx, rname, rtype, + regmode, iname, field, end=" ") # see Mode field https://libre-soc.org/openpower/sv/svp64/ # XXX TODO: the following is a bit of a laborious repeated @@ -368,7 +375,8 @@ class SVP64Asm: field = (field << 2) | cr_subfield # capture the extra field info - print ("=>", "%5s" % bin(sv_extra), field) + if self.verbose: + print ("=>", "%5s" % bin(sv_extra), field) extras[extra_idx] = sv_extra # append altered field value to v3.0b, differs for LDST @@ -377,8 +385,9 @@ class SVP64Asm: else: v30b_newfields.append(str(field)) - print ("new v3.0B fields", v30b_op, v30b_newfields) - print ("extras", extras) + if self.verbose: + print ("new v3.0B fields", v30b_op, v30b_newfields) + print ("extras", extras) # rright. now we have all the info. start creating SVP64 RM svp64_rm = SVP64RMFields() @@ -615,23 +624,27 @@ class SVP64Asm: # nice debug printout. (and now for something completely different) # https://youtu.be/u0WOIwlXE9g?t=146 svp64_rm_value = svp64_rm.spr.value - print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value)) - print (" mmode 0 :", bin(mmode)) - print (" pmask 1-3 :", bin(pmask)) - print (" dstwid 4-5 :", bin(destwid)) - print (" srcwid 6-7 :", bin(srcwid)) - print (" subvl 8-9 :", bin(subvl)) - print (" mode 19-23:", bin(mode)) + if self.verbose: + print ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value)) + print (" mmode 0 :", bin(mmode)) + print (" pmask 1-3 :", bin(pmask)) + print (" dstwid 4-5 :", bin(destwid)) + print (" srcwid 6-7 :", bin(srcwid)) + print (" subvl 8-9 :", bin(subvl)) + print (" mode 19-23:", bin(mode)) offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits for idx, sv_extra in extras.items(): if idx is None: continue start = (10+idx*offs) end = start + offs-1 - print (" extra%d %2d-%2d:" % (idx, start, end), - bin(sv_extra)) + if self.verbose: + print (" extra%d %2d-%2d:" % (idx, start, end), + bin(sv_extra)) if ptype == '2P': - print (" smask 16-17:", bin(smask)) - print () + if self.verbose: + print (" smask 16-17:", bin(smask)) + if self.verbose: + print () # first, construct the prefix from its subfields svp64_prefix = SVP64PrefixFields() @@ -643,7 +656,8 @@ class SVP64Asm: rc = '.' if rc_mode else '' yield ".long 0x%x" % svp64_prefix.insn.value yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields)) - print ("new v3.0B fields", v30b_op, v30b_newfields) + if self.verbose: + print ("new v3.0B fields", v30b_op, v30b_newfields) if __name__ == '__main__': lst = ['slw 3, 1, 4', -- 2.30.2