From 1368b914e93a3af332f787d3d41c106d11bb90da Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 5 Jan 2021 22:09:57 -0500 Subject: [PATCH] sim: testsuite: flatten tree Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine. --- sim/testsuite/ChangeLog | 5 +++++ sim/testsuite/Makefile.in | 1 - sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/{sim => }/arm/ChangeLog | 0 sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/{sim => }/arm/allinsn.exp | 0 sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0 sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/{sim => }/bfin/ChangeLog | 0 sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/{sim => }/bfin/allinsn.exp | 0 sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => 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=> }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename 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=> }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbul.cgs (100%) rename sim/testsuite/{sim => }/frv/fbule.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fckge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckle.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckne.cgs (100%) rename sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) rename sim/testsuite/{sim => }/frv/grloop.ms (100%) rename sim/testsuite/{sim => }/frv/hello.ms (100%) rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%) diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index fc5806e36b6..4271705fb30 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2021-01-15 Mike Frysinger + + * Makefile.in (site.exp): Delete tool setting. + * sim/*/: Move subdirs up a directory. + 2021-01-15 Mike Frysinger * configure, configure.ac: Delete. diff --git a/sim/testsuite/Makefile.in b/sim/testsuite/Makefile.in index 1f75db6a553..1e4604cea68 100644 --- a/sim/testsuite/Makefile.in +++ b/sim/testsuite/Makefile.in @@ -127,7 +127,6 @@ site.exp: Makefile @echo '## these variables are automatically generated by make ##' > $@-t @echo '# Do not edit here. If you wish to override these values' >> $@-t @echo '# edit the last section' >> $@-t - @echo 'set tool sim' >> $@-t @echo 'set srcdir $(srcdir)' >> $@-t @echo 'set objdir' `pwd` >> $@-t @echo 'set arch $(arch)' >> $@-t diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/aarch64/ChangeLog similarity index 100% rename from sim/testsuite/sim/aarch64/ChangeLog rename to sim/testsuite/aarch64/ChangeLog diff --git a/sim/testsuite/sim/aarch64/adds.s b/sim/testsuite/aarch64/adds.s similarity index 100% rename from sim/testsuite/sim/aarch64/adds.s rename to sim/testsuite/aarch64/adds.s diff --git a/sim/testsuite/sim/aarch64/addv.s b/sim/testsuite/aarch64/addv.s similarity index 100% rename from sim/testsuite/sim/aarch64/addv.s rename to sim/testsuite/aarch64/addv.s diff --git a/sim/testsuite/sim/aarch64/allinsn.exp b/sim/testsuite/aarch64/allinsn.exp similarity index 100% rename from sim/testsuite/sim/aarch64/allinsn.exp rename to sim/testsuite/aarch64/allinsn.exp diff --git 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b/sim/testsuite/bfin/c_dsp32shiftim_lmix.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dsp32shiftim_lmix.s rename to sim/testsuite/bfin/c_dsp32shiftim_lmix.s diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s b/sim/testsuite/bfin/c_dsp32shiftim_rot.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dsp32shiftim_rot.s rename to sim/testsuite/bfin/c_dsp32shiftim_rot.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s b/sim/testsuite/bfin/c_dspldst_ld_dr_i.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_ld_dr_i.s rename to sim/testsuite/bfin/c_dspldst_ld_dr_i.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s b/sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_ld_dr_ipp.s rename to sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_ld_dr_ippm.s b/sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s similarity index 100% rename from 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sim/testsuite/bfin/c_dspldst_ld_drlo_ipp.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s b/sim/testsuite/bfin/c_dspldst_st_dr_i.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_dr_i.s rename to sim/testsuite/bfin/c_dspldst_st_dr_i.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s b/sim/testsuite/bfin/c_dspldst_st_dr_ipp.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_dr_ipp.s rename to sim/testsuite/bfin/c_dspldst_st_dr_ipp.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s b/sim/testsuite/bfin/c_dspldst_st_dr_ippm.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_dr_ippm.s rename to sim/testsuite/bfin/c_dspldst_st_dr_ippm.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s b/sim/testsuite/bfin/c_dspldst_st_drhi_i.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_drhi_i.s rename to sim/testsuite/bfin/c_dspldst_st_drhi_i.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s b/sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_drhi_ipp.s rename to sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s b/sim/testsuite/bfin/c_dspldst_st_drlo_i.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_drlo_i.s rename to sim/testsuite/bfin/c_dspldst_st_drlo_i.s diff --git a/sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s b/sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s similarity index 100% rename from sim/testsuite/sim/bfin/c_dspldst_st_drlo_ipp.s rename to sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s diff --git a/sim/testsuite/sim/bfin/c_except_illopcode.S b/sim/testsuite/bfin/c_except_illopcode.S similarity index 100% rename from sim/testsuite/sim/bfin/c_except_illopcode.S rename to sim/testsuite/bfin/c_except_illopcode.S diff --git a/sim/testsuite/sim/bfin/c_except_sys_sstep.S b/sim/testsuite/bfin/c_except_sys_sstep.S similarity index 100% rename from sim/testsuite/sim/bfin/c_except_sys_sstep.S rename to sim/testsuite/bfin/c_except_sys_sstep.S diff --git a/sim/testsuite/sim/bfin/c_except_user_mode.S b/sim/testsuite/bfin/c_except_user_mode.S similarity index 100% rename from sim/testsuite/sim/bfin/c_except_user_mode.S rename to sim/testsuite/bfin/c_except_user_mode.S diff --git a/sim/testsuite/sim/bfin/c_interr_disable.S b/sim/testsuite/bfin/c_interr_disable.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_disable.S rename to sim/testsuite/bfin/c_interr_disable.S diff --git a/sim/testsuite/sim/bfin/c_interr_disable_enable.S b/sim/testsuite/bfin/c_interr_disable_enable.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_disable_enable.S rename to sim/testsuite/bfin/c_interr_disable_enable.S diff --git a/sim/testsuite/sim/bfin/c_interr_excpt.S b/sim/testsuite/bfin/c_interr_excpt.S similarity index 100% rename from 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a/sim/testsuite/sim/bfin/c_interr_pending_2.S b/sim/testsuite/bfin/c_interr_pending_2.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_pending_2.S rename to sim/testsuite/bfin/c_interr_pending_2.S diff --git a/sim/testsuite/sim/bfin/c_interr_timer.S b/sim/testsuite/bfin/c_interr_timer.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_timer.S rename to sim/testsuite/bfin/c_interr_timer.S diff --git a/sim/testsuite/sim/bfin/c_interr_timer_reload.S b/sim/testsuite/bfin/c_interr_timer_reload.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_timer_reload.S rename to sim/testsuite/bfin/c_interr_timer_reload.S diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tcount.S b/sim/testsuite/bfin/c_interr_timer_tcount.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_timer_tcount.S rename to sim/testsuite/bfin/c_interr_timer_tcount.S diff --git a/sim/testsuite/sim/bfin/c_interr_timer_tscale.S b/sim/testsuite/bfin/c_interr_timer_tscale.S similarity index 100% rename from sim/testsuite/sim/bfin/c_interr_timer_tscale.S rename to sim/testsuite/bfin/c_interr_timer_tscale.S diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s b/sim/testsuite/bfin/c_ldimmhalf_dreg.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldimmhalf_dreg.s rename to sim/testsuite/bfin/c_ldimmhalf_dreg.s diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s b/sim/testsuite/bfin/c_ldimmhalf_drhi.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s rename to sim/testsuite/bfin/c_ldimmhalf_drhi.s diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s b/sim/testsuite/bfin/c_ldimmhalf_drlo.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldimmhalf_drlo.s rename to sim/testsuite/bfin/c_ldimmhalf_drlo.s diff --git a/sim/testsuite/sim/bfin/c_ldimmhalf_h_dr.s b/sim/testsuite/bfin/c_ldimmhalf_h_dr.s similarity index 100% rename from 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to sim/testsuite/bfin/c_ldstidxl_ld_dr_b.s diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_h.s rename to sim/testsuite/bfin/c_ldstidxl_ld_dr_h.s diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xb.s rename to sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s b/sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldstidxl_ld_dr_xh.s rename to sim/testsuite/bfin/c_ldstidxl_ld_dr_xh.s diff --git a/sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s b/sim/testsuite/bfin/c_ldstidxl_ld_dreg.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ldstidxl_ld_dreg.s rename to sim/testsuite/bfin/c_ldstidxl_ld_dreg.s diff --git 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a/sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s b/sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s similarity index 100% rename from sim/testsuite/sim/bfin/c_multi_issue_dsp_ldst_2.s rename to sim/testsuite/bfin/c_multi_issue_dsp_ldst_2.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s b/sim/testsuite/bfin/c_progctrl_call_pcpr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_call_pcpr.s rename to sim/testsuite/bfin/c_progctrl_call_pcpr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_call_pr.s b/sim/testsuite/bfin/c_progctrl_call_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_call_pr.s rename to sim/testsuite/bfin/c_progctrl_call_pr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S b/sim/testsuite/bfin/c_progctrl_clisti_interr.S similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_clisti_interr.S rename to sim/testsuite/bfin/c_progctrl_clisti_interr.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S b/sim/testsuite/bfin/c_progctrl_csync_mmr.S similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_csync_mmr.S rename to sim/testsuite/bfin/c_progctrl_csync_mmr.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S b/sim/testsuite/bfin/c_progctrl_except_rtx.S similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_except_rtx.S rename to sim/testsuite/bfin/c_progctrl_except_rtx.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_excpt.S b/sim/testsuite/bfin/c_progctrl_excpt.S similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_excpt.S rename to sim/testsuite/bfin/c_progctrl_excpt.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s b/sim/testsuite/bfin/c_progctrl_jump_pcpr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s rename to sim/testsuite/bfin/c_progctrl_jump_pcpr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s b/sim/testsuite/bfin/c_progctrl_jump_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_jump_pr.s rename to sim/testsuite/bfin/c_progctrl_jump_pr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_nop.s b/sim/testsuite/bfin/c_progctrl_nop.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_nop.s rename to sim/testsuite/bfin/c_progctrl_nop.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S b/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S rename to sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_rts.s b/sim/testsuite/bfin/c_progctrl_rts.s similarity index 100% rename from sim/testsuite/sim/bfin/c_progctrl_rts.s rename to sim/testsuite/bfin/c_progctrl_rts.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s b/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s rename to sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s b/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s rename to sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s b/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s rename to sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s b/sim/testsuite/bfin/c_pushpopmultiple_dp.s similarity index 100% rename from sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s rename to sim/testsuite/bfin/c_pushpopmultiple_dp.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s b/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s similarity index 100% rename from sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s rename to sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s b/sim/testsuite/bfin/c_pushpopmultiple_dreg.s similarity index 100% rename from sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s rename to sim/testsuite/bfin/c_pushpopmultiple_dreg.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s b/sim/testsuite/bfin/c_pushpopmultiple_preg.s similarity index 100% rename from sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s rename to sim/testsuite/bfin/c_pushpopmultiple_preg.s diff --git a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s b/sim/testsuite/bfin/c_regmv_acc_acc.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_acc_acc.s rename to sim/testsuite/bfin/c_regmv_acc_acc.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s b/sim/testsuite/bfin/c_regmv_dag_lz_dep.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s rename to sim/testsuite/bfin/c_regmv_dag_lz_dep.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s b/sim/testsuite/bfin/c_regmv_dr_acc_acc.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s rename to sim/testsuite/bfin/c_regmv_dr_acc_acc.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s b/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s rename to sim/testsuite/bfin/c_regmv_dr_dep_nostall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s b/sim/testsuite/bfin/c_regmv_dr_dr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dr_dr.s rename to sim/testsuite/bfin/c_regmv_dr_dr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s b/sim/testsuite/bfin/c_regmv_dr_imlb.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dr_imlb.s rename to sim/testsuite/bfin/c_regmv_dr_imlb.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s b/sim/testsuite/bfin/c_regmv_dr_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_dr_pr.s rename to sim/testsuite/bfin/c_regmv_dr_pr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s b/sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s rename to sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s b/sim/testsuite/bfin/c_regmv_imlb_dep_stall.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_imlb_dep_stall.s rename to sim/testsuite/bfin/c_regmv_imlb_dep_stall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dr.s b/sim/testsuite/bfin/c_regmv_imlb_dr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_imlb_dr.s rename to sim/testsuite/bfin/c_regmv_imlb_dr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s b/sim/testsuite/bfin/c_regmv_imlb_imlb.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_imlb_imlb.s rename to sim/testsuite/bfin/c_regmv_imlb_imlb.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_pr.s b/sim/testsuite/bfin/c_regmv_imlb_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_imlb_pr.s rename to sim/testsuite/bfin/c_regmv_imlb_pr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s b/sim/testsuite/bfin/c_regmv_pr_dep_nostall.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_pr_dep_nostall.s rename to sim/testsuite/bfin/c_regmv_pr_dep_nostall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s b/sim/testsuite/bfin/c_regmv_pr_dep_stall.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_pr_dep_stall.s rename to sim/testsuite/bfin/c_regmv_pr_dep_stall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_dr.s b/sim/testsuite/bfin/c_regmv_pr_dr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_pr_dr.s rename to sim/testsuite/bfin/c_regmv_pr_dr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_imlb.s b/sim/testsuite/bfin/c_regmv_pr_imlb.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_pr_imlb.s rename to sim/testsuite/bfin/c_regmv_pr_imlb.s diff --git a/sim/testsuite/sim/bfin/c_regmv_pr_pr.s b/sim/testsuite/bfin/c_regmv_pr_pr.s similarity index 100% rename from sim/testsuite/sim/bfin/c_regmv_pr_pr.s rename to sim/testsuite/bfin/c_regmv_pr_pr.s diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S b/sim/testsuite/bfin/c_seq_ac_raise_mv.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ac_raise_mv.S rename to sim/testsuite/bfin/c_seq_ac_raise_mv.S diff --git a/sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S b/sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ac_raise_mv_ppop.S rename to sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S b/sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ac_regmv_pushpop.S rename to sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S diff --git a/sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S b/sim/testsuite/bfin/c_seq_dec_raise_pushpop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_dec_raise_pushpop.S rename to sim/testsuite/bfin/c_seq_dec_raise_pushpop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_brcc_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_call_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_call_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_j_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_raise_brcc_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_raise_call_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_raise_call_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S b/sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex1_raise_j_mv_pop.S rename to sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex2_brcc_mp_mv_pop.S b/sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S similarity index 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sim/testsuite/sim/bfin/c_seq_ex2_raise_mmrj_mvpop.S rename to sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex3_ls_brcc_mvp.S rename to sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex3_ls_mmr_mvp.S rename to sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S b/sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex3_ls_mmrj_mvp.S rename to sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S b/sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S rename to sim/testsuite/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_wb_cs_lsmmrj_mvp.S rename to sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S rename to sim/testsuite/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_wb_rti_lsmmrj_mvp.S rename to sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_wb_rtn_lsmmrj_mvp.S rename to sim/testsuite/bfin/c_seq_wb_rtn_lsmmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S b/sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S similarity index 100% rename from sim/testsuite/sim/bfin/c_seq_wb_rtx_lsmmrj_mvp.S rename to sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S diff --git a/sim/testsuite/sim/bfin/c_ujump.s b/sim/testsuite/bfin/c_ujump.s similarity index 100% rename from sim/testsuite/sim/bfin/c_ujump.s rename to sim/testsuite/bfin/c_ujump.s diff --git a/sim/testsuite/sim/bfin/cc-alu.S b/sim/testsuite/bfin/cc-alu.S similarity index 100% rename from sim/testsuite/sim/bfin/cc-alu.S rename to sim/testsuite/bfin/cc-alu.S diff --git a/sim/testsuite/sim/bfin/cc-astat-bits.s b/sim/testsuite/bfin/cc-astat-bits.s similarity index 100% rename from sim/testsuite/sim/bfin/cc-astat-bits.s rename to sim/testsuite/bfin/cc-astat-bits.s diff --git a/sim/testsuite/sim/bfin/cc0.s b/sim/testsuite/bfin/cc0.s similarity index 100% rename from sim/testsuite/sim/bfin/cc0.s rename to sim/testsuite/bfin/cc0.s diff --git a/sim/testsuite/sim/bfin/cc1.s b/sim/testsuite/bfin/cc1.s similarity index 100% rename from sim/testsuite/sim/bfin/cc1.s rename to sim/testsuite/bfin/cc1.s diff --git a/sim/testsuite/sim/bfin/cc5.S b/sim/testsuite/bfin/cc5.S similarity index 100% rename from sim/testsuite/sim/bfin/cc5.S rename to sim/testsuite/bfin/cc5.S diff --git a/sim/testsuite/sim/bfin/cec-exact-exception.S b/sim/testsuite/bfin/cec-exact-exception.S similarity index 100% rename from sim/testsuite/sim/bfin/cec-exact-exception.S rename to sim/testsuite/bfin/cec-exact-exception.S diff --git a/sim/testsuite/sim/bfin/cec-ifetch.S b/sim/testsuite/bfin/cec-ifetch.S similarity index 100% rename from sim/testsuite/sim/bfin/cec-ifetch.S rename to sim/testsuite/bfin/cec-ifetch.S diff --git a/sim/testsuite/sim/bfin/cec-multi-pending.S b/sim/testsuite/bfin/cec-multi-pending.S similarity index 100% rename from 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to sim/testsuite/frv/mqxmacxhs.cgs diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/frv/mrdacc.cgs similarity index 100% rename from sim/testsuite/sim/frv/mrdacc.cgs rename to sim/testsuite/frv/mrdacc.cgs diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/frv/mrdaccg.cgs similarity index 100% rename from sim/testsuite/sim/frv/mrdaccg.cgs rename to sim/testsuite/frv/mrdaccg.cgs diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/frv/mrotli.cgs similarity index 100% rename from sim/testsuite/sim/frv/mrotli.cgs rename to sim/testsuite/frv/mrotli.cgs diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/frv/mrotri.cgs similarity index 100% rename from sim/testsuite/sim/frv/mrotri.cgs rename to sim/testsuite/frv/mrotri.cgs diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/frv/msaths.cgs similarity index 100% rename from sim/testsuite/sim/frv/msaths.cgs rename to sim/testsuite/frv/msaths.cgs diff --git a/sim/testsuite/sim/frv/msathu.cgs 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to sim/testsuite/frv/sracc.cgs diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/frv/srai.cgs similarity index 100% rename from sim/testsuite/sim/frv/srai.cgs rename to sim/testsuite/frv/srai.cgs diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/frv/sraicc.cgs similarity index 100% rename from sim/testsuite/sim/frv/sraicc.cgs rename to sim/testsuite/frv/sraicc.cgs diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/frv/srl.cgs similarity index 100% rename from sim/testsuite/sim/frv/srl.cgs rename to sim/testsuite/frv/srl.cgs diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/frv/srlcc.cgs similarity index 100% rename from sim/testsuite/sim/frv/srlcc.cgs rename to sim/testsuite/frv/srlcc.cgs diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/frv/srli.cgs similarity index 100% rename from sim/testsuite/sim/frv/srli.cgs rename to sim/testsuite/frv/srli.cgs diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/frv/srlicc.cgs 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from sim/testsuite/sim/frv/subi.cgs rename to sim/testsuite/frv/subi.cgs diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/frv/subicc.cgs similarity index 100% rename from sim/testsuite/sim/frv/subicc.cgs rename to sim/testsuite/frv/subicc.cgs diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/frv/subx.cgs similarity index 100% rename from sim/testsuite/sim/frv/subx.cgs rename to sim/testsuite/frv/subx.cgs diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/frv/subxcc.cgs similarity index 100% rename from sim/testsuite/sim/frv/subxcc.cgs rename to sim/testsuite/frv/subxcc.cgs diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/frv/subxi.cgs similarity index 100% rename from sim/testsuite/sim/frv/subxi.cgs rename to sim/testsuite/frv/subxi.cgs diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/frv/subxicc.cgs similarity index 100% rename from sim/testsuite/sim/frv/subxicc.cgs rename to sim/testsuite/frv/subxicc.cgs diff --git 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a/sim/testsuite/sim/v850/sar.cgs b/sim/testsuite/v850/sar.cgs similarity index 100% rename from sim/testsuite/sim/v850/sar.cgs rename to sim/testsuite/v850/sar.cgs diff --git a/sim/testsuite/sim/v850/satadd.cgs b/sim/testsuite/v850/satadd.cgs similarity index 100% rename from sim/testsuite/sim/v850/satadd.cgs rename to sim/testsuite/v850/satadd.cgs diff --git a/sim/testsuite/sim/v850/satsub.cgs b/sim/testsuite/v850/satsub.cgs similarity index 100% rename from sim/testsuite/sim/v850/satsub.cgs rename to sim/testsuite/v850/satsub.cgs diff --git a/sim/testsuite/sim/v850/satsubi.cgs b/sim/testsuite/v850/satsubi.cgs similarity index 100% rename from sim/testsuite/sim/v850/satsubi.cgs rename to sim/testsuite/v850/satsubi.cgs diff --git a/sim/testsuite/sim/v850/satsubr.cgs b/sim/testsuite/v850/satsubr.cgs similarity index 100% rename from sim/testsuite/sim/v850/satsubr.cgs rename to sim/testsuite/v850/satsubr.cgs diff --git a/sim/testsuite/sim/v850/shl.cgs b/sim/testsuite/v850/shl.cgs similarity index 100% rename from sim/testsuite/sim/v850/shl.cgs rename to sim/testsuite/v850/shl.cgs diff --git a/sim/testsuite/sim/v850/shr.cgs b/sim/testsuite/v850/shr.cgs similarity index 100% rename from sim/testsuite/sim/v850/shr.cgs rename to sim/testsuite/v850/shr.cgs diff --git a/sim/testsuite/sim/v850/testutils.cgs b/sim/testsuite/v850/testutils.cgs similarity index 100% rename from sim/testsuite/sim/v850/testutils.cgs rename to sim/testsuite/v850/testutils.cgs diff --git a/sim/testsuite/sim/v850/testutils.inc b/sim/testsuite/v850/testutils.inc similarity index 100% rename from sim/testsuite/sim/v850/testutils.inc rename to sim/testsuite/v850/testutils.inc -- 2.30.2