From 137b89c88c2e00639cb4f55857e7ac61c961a5b1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 17:32:56 +0100 Subject: [PATCH] use common TestCase in shift_rot --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index f73f9b23..cab58845 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -12,18 +12,12 @@ from soc.simulator.program import Program from soc.decoder.isa.all import ISA +from soc.fu.test.common import TestCase from soc.fu.shift_rot.pipeline import ShiftRotBasePipe from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec import random -class TestCase: - def __init__(self, program, regs, sprs, name): - self.program = program - self.regs = regs - self.sprs = sprs - self.name = name - def get_cu_inputs(dec2, sim): """naming (res) must conform to ShiftRotFunctionUnit input regspec @@ -117,8 +111,8 @@ class ShiftRotTestCase(FHDLTestCase): def __init__(self, name): super().__init__(name) self.test_name = name - def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): - tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None): + tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) test_data.append(tc) -- 2.30.2