From 138678ae11646c89cfb597ea9b5cef9433f04bcb Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Jul 2020 16:20:12 +0100
Subject: [PATCH] ordering of tests for OP_ATTN needed shuffling.  seems to be
 working

---
 src/soc/decoder/isa/caller.py    | 11 +++++++----
 src/soc/simple/core.py           | 27 ++++++++++++++-------------
 src/soc/simple/test/test_core.py |  2 +-
 3 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7d73551a..133d4b09 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -532,6 +532,13 @@ class ISACaller:
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
         asmop = yield from self.get_assembly_name()
         print  ("call", name, asmop)
+
+        # check halted condition
+        if name == 'attn':
+            self.halted = True
+            return
+
+        # check illegal instruction
         illegal = False
         if name not in ['mtcrf', 'mtocrf']:
             illegal = name != asmop
@@ -543,10 +550,6 @@ class ISACaller:
             self.pc.update(self.namespace)
             return
 
-        if name == 'attn':
-            self.halted = True
-            return
-
         info = self.instrs[name]
         yield from self.prep_namespace(info.form, info.op_fields)
 
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index e8382f5d..382a8588 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -126,19 +126,20 @@ class NonProductionCore(Elaboratable):
         can_run = Signal(reset_less=True)
         comb += can_run.eq(self.ivalid_i & ~core_stopped)
 
-        # connect up instructions.  only one is enabled at any given time
-        for funame, fu in fus.items():
-            fnunit = fu.fnunit.value
-            enable = Signal(name="en_%s" % funame, reset_less=True)
-            comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool() & can_run)
-
-            # run this FunctionUnit if enabled, except if the instruction
-            # is "attn" in which case we HALT.
-            with m.If(enable):
-                with m.If(dec2.e.do.insn_type == InternalOp.OP_ATTN):
-                    # check for ATTN: halt if true
-                    m.d.sync += core_stopped.eq(1)
-                with m.Else():
+        # check for ATTN: halt if true
+        with m.If(self.ivalid_i & (dec2.e.do.insn_type == InternalOp.OP_ATTN)):
+            m.d.sync += core_stopped.eq(1)
+
+        with m.Else():
+            # connect up instructions.  only one is enabled at any given time
+            for funame, fu in fus.items():
+                fnunit = fu.fnunit.value
+                enable = Signal(name="en_%s" % funame, reset_less=True)
+                comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool() & can_run)
+
+                # run this FunctionUnit if enabled, except if the instruction
+                # is "attn" in which case we HALT.
+                with m.If(enable):
                     # route operand, issue, busy, read flags and mask to FU
                     comb += fu.oper_i.eq_from_execute1(dec2.e)
                     comb += fu.issue_i.eq(self.issue_i)
diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 69445548..a341cfe5 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -136,7 +136,7 @@ def wait_for_busy_hi(cu):
         if busy_o or terminated_o:
             print("busy/terminated:", busy_o, terminated_o)
             break
-        print("!busy",)
+        print("!busy", busy_o, terminated_o)
         yield
 
 def set_issue(core, dec2, sim):
-- 
2.30.2