From 1388088240159732d97069cdb692ba7429700a43 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 21 Jan 2020 14:08:36 +0100 Subject: [PATCH] cores/icap: add add_timing_constraints method --- litex/soc/cores/icap.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py index 5d7626b1..feab751b 100644 --- a/litex/soc/cores/icap.py +++ b/litex/soc/cores/icap.py @@ -73,6 +73,10 @@ class ICAP(Module, AutoCSR): ) ] + def add_timing_constraints(self, platform, sys_clk_freq, sys_clk): + platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq) + platform.add_false_path_constraints(self.cd_icap.clk, sys_clk) + class ICAPBitstream(Module, AutoCSR): """ICAP Bitstream @@ -130,3 +134,7 @@ class ICAPBitstream(Module, AutoCSR): i_I=Cat(*[_i[8*i:8*(i+1)][::-1] for i in range(4)]), ) ] + + def add_timing_constraints(self, platform, sys_clk_freq, sys_clk): + platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq) + platform.add_false_path_constraints(self.cd_icap.clk, sys_clk) -- 2.30.2