From 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Tue, 21 Sep 2010 23:07:35 -0700
Subject: [PATCH] stats: update stats for previous cset Coherence protocol
 change basically got rid of UpgradeReqs in L2 caches, other minor related
 cache stat changes.

---
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/simout  |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  649 +++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  181 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  179 +-
 .../ref/sparc/linux/o3-timing/config.ini      |    2 +-
 .../00.gzip/ref/sparc/linux/o3-timing/simout  |   12 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  649 +++---
 .../ref/sparc/linux/simple-timing/config.ini  |    2 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  195 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |   12 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  179 +-
 .../alpha/linux/tsunami-o3-dual/config.ini    |   12 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |   16 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 2000 +++++++++--------
 .../ref/alpha/linux/tsunami-o3/config.ini     |   12 +-
 .../ref/alpha/linux/tsunami-o3/simout         |   14 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      |  996 ++++----
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../10.mcf/ref/arm/linux/simple-timing/simout |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  205 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  223 +-
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../10.mcf/ref/x86/linux/simple-timing/simout |   12 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  187 +-
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  181 +-
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |   12 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  211 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  627 +++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  139 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../30.eon/ref/arm/linux/simple-timing/simout |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  135 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../ref/alpha/tru64/o3-timing/simout          |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  620 +++--
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  174 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  203 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    2 +-
 .../ref/alpha/tru64/inorder-timing/simout     |   12 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  287 ++-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../ref/alpha/tru64/o3-timing/simout          |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  661 +++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  205 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  205 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    2 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  225 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |   12 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  663 +++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  183 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |   12 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  183 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |   12 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  183 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    2 +-
 .../ref/alpha/tru64/inorder-timing/simout     |   13 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  256 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    2 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |   13 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  580 +++--
 .../ref/alpha/tru64/simple-timing/config.ini  |    2 +-
 .../ref/alpha/tru64/simple-timing/simout      |   14 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  142 +-
 .../ref/arm/linux/simple-timing/config.ini    |    2 +-
 .../ref/arm/linux/simple-timing/simout        |   14 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  126 +-
 .../ref/x86/linux/simple-timing/config.ini    |    2 +-
 .../ref/x86/linux/simple-timing/simout        |   14 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   95 +-
 .../tsunami-simple-atomic-dual/config.ini     |   12 +-
 .../linux/tsunami-simple-atomic-dual/simout   |   12 +-
 .../tsunami-simple-atomic-dual/stats.txt      |  260 +--
 .../linux/tsunami-simple-atomic/config.ini    |   12 +-
 .../alpha/linux/tsunami-simple-atomic/simout  |   12 +-
 .../linux/tsunami-simple-atomic/stats.txt     |  150 +-
 .../tsunami-simple-timing-dual/config.ini     |   12 +-
 .../linux/tsunami-simple-timing-dual/simout   |   16 +-
 .../tsunami-simple-timing-dual/stats.txt      | 1243 +++++-----
 .../system.terminal                           |    2 +-
 .../linux/tsunami-simple-timing/config.ini    |   12 +-
 .../alpha/linux/tsunami-simple-timing/simout  |   14 +-
 .../linux/tsunami-simple-timing/stats.txt     |  612 +++--
 .../50.memtest/ref/alpha/linux/memtest/simerr |  146 +-
 .../50.memtest/ref/alpha/linux/memtest/simout |   12 +-
 .../ref/alpha/linux/memtest/stats.txt         | 1590 ++++++-------
 115 files changed, 8078 insertions(+), 8472 deletions(-)

diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 850b52f90..93b3428c5 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 9bd144353..d26bd1d3b 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:05
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:56:01
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -46,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 169506496500 because target called exit()
+Exiting @ tick 165376986500 because target called exit()
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 29244fba0..13a46d5d3 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,340 +1,340 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 178555                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207544                       # Number of bytes of host memory used
-host_seconds                                  3167.39                       # Real time elapsed on the host
-host_tick_rate                               53516139                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 264030                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193748                       # Number of bytes of host memory used
+host_seconds                                  2142.00                       # Real time elapsed on the host
+host_tick_rate                               77206740                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   565552443                       # Number of instructions simulated
-sim_seconds                                  0.169506                       # Number of seconds simulated
-sim_ticks                                169506496500                       # Number of ticks simulated
+sim_seconds                                  0.165377                       # Number of seconds simulated
+sim_ticks                                165376986500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 64068954                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              71556079                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                 188                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            4120910                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           70589657                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 76519042                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1672225                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits                 63929788                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              71429024                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 197                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            4120838                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           70454375                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 76396550                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1676108                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               62547159                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          19702213                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events          20033371                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    327417755                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.838193                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.277454                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    320816297                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.876017                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.306184                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    105871733     32.34%     32.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    108541066     33.15%     65.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     36996526     11.30%     76.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     11988281      3.66%     80.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     10398233      3.18%     83.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     21777635      6.65%     90.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      9735285      2.97%     93.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      2406783      0.74%     93.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     19702213      6.02%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    102501444     31.95%     31.95% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    105613320     32.92%     64.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     36739083     11.45%     76.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     11050019      3.44%     79.77% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     10174748      3.17%     82.94% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     21768321      6.79%     89.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     10744082      3.35%     93.07% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      2191909      0.68%     93.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     20033371      6.24%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    327417755                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total    320816297                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 601856963                       # Number of instructions committed
 system.cpu.commit.COM:loads                 115049510                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  154862033                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           4120073                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts           4120001                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        63088611                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        61749735                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
-system.cpu.cpi                               0.599437                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.599437                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.584833                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.584833                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            4                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                4                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          116877204                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7693.277195                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              116024078                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    16646128000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.007299                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               853126                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            634854                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1679227000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001868                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          218272                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses          115012927                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7392.342173                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              114228619                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    11757056000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.006819                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               784308                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            566126                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   1612876000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001897                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          218182                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              37146976                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   73589663391                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.058410                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             2304345                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1968193                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  11570226999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.008521                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         336152                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  7088.486726                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 323.627554                       # Average number of references to valid blocks.
+system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              38301940                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   17132785891                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.029134                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1149381                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits           892463                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   2839893498                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006512                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         256918                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6663.699115                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 321.049385                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs               113                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs       800999                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       235000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs       752998                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       224000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           156328525                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 28578.502032                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               153171054                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     90235791391                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.020198                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               3157471                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2603047                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  13249453999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003547                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           554424                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           154464248                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 14940.273173                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9372.278463                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               152530559                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     28889841891                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.012519                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1933689                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            1458589                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   4452769498                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.003076                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           475100                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999568                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.232018                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          156328525                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 28578.502032                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.999558                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.188781                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          154464248                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 14940.273173                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9372.278463                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              153171054                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    90235791391                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.020198                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              3157471                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2603047                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  13249453999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003547                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          554424                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              152530559                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    28889841891                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.012519                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1933689                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           1458589                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   4452769498                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.003076                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          475100                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 471007                       # number of replacements
-system.cpu.dcache.sampled_refs                 475103                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 471004                       # number of replacements
+system.cpu.dcache.sampled_refs                 475100                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.232018                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                153756422                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              126427000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   336082                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       53096224                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            870                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       4174977                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       691367918                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         145684312                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          123209609                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        10007520                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           3007                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        5427610                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                163170180                       # DTB accesses
+system.cpu.dcache.tagsinuse               4094.188781                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                152530563                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              126404000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   423151                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       48113828                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred            871                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       4177876                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       689990711                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         144277716                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          122985866                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         9844039                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts           3043                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        5438887                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                163094811                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    163108618                       # DTB hits
-system.cpu.dtb.data_misses                      61562                       # DTB misses
+system.cpu.dtb.data_hits                    163045966                       # DTB hits
+system.cpu.dtb.data_misses                      48845                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                122378622                       # DTB read accesses
+system.cpu.dtb.read_accesses                122278185                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    122354151                       # DTB read hits
-system.cpu.dtb.read_misses                      24471                       # DTB read misses
-system.cpu.dtb.write_accesses                40791558                       # DTB write accesses
+system.cpu.dtb.read_hits                    122255138                       # DTB read hits
+system.cpu.dtb.read_misses                      23047                       # DTB read misses
+system.cpu.dtb.write_accesses                40816626                       # DTB write accesses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                    40754467                       # DTB write hits
-system.cpu.dtb.write_misses                     37091                       # DTB write misses
-system.cpu.fetch.Branches                    76519042                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  65743933                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     196171036                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               1323544                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      700543147                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                 4180854                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.225711                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           65743933                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           65741179                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.066420                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          337425275                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.076143                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.069329                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits                    40790828                       # DTB write hits
+system.cpu.dtb.write_misses                     25798                       # DTB write misses
+system.cpu.fetch.Branches                    76396550                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  65649275                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     195872330                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               1325100                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      699185184                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                 4170349                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.230977                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           65649275                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           65605896                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        2.113913                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          330660336                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.114512                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.085107                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                206998212     61.35%     61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 10205574      3.02%     64.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 16013127      4.75%     69.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 13976667      4.14%     73.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 12062274      3.57%     76.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13987466      4.15%     80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5886424      1.74%     82.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3487900      1.03%     83.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 54807631     16.24%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                200437318     60.62%     60.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 10372140      3.14%     63.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15863919      4.80%     68.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 13948828      4.22%     72.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 12077397      3.65%     76.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13850642      4.19%     80.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5888624      1.78%     82.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3427564      1.04%     83.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 54793904     16.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            337425275                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses           65743933                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36198.392555                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               65742751                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       42786500                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total            330660336                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses           65649275                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36269.949066                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               65648097                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       42726000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1182                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               270                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     32385000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                 1178                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               268                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     32327500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             912                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses             910                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               72086.349781                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               72140.765934                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            65743933                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36198.392555                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                65742751                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        42786500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses            65649275                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36269.949066                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                65648097                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        42726000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000018                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1182                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                270                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     32385000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                  1178                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                268                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     32327500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              912                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses              910                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.379446                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            777.105869                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           65743933                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36198.392555                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35509.868421                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.378879                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            775.944948                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           65649275                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36269.949066                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               65742751                       # number of overall hits
-system.cpu.icache.overall_miss_latency       42786500                       # number of overall miss cycles
+system.cpu.icache.overall_hits               65648097                       # number of overall hits
+system.cpu.icache.overall_miss_latency       42726000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000018                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1182                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               270                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     32385000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                 1178                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               268                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     32327500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             912                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses             910                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                     36                       # number of replacements
-system.cpu.icache.sampled_refs                    912                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                     32                       # number of replacements
+system.cpu.icache.sampled_refs                    910                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                777.105869                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 65742751                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                775.944948                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 65648097                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1587719                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 67446690                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      43287555                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.768234                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    164109637                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   41186586                       # Number of stores executed
+system.cpu.idleCycles                           93638                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 67433622                       # Number of branches executed
+system.cpu.iew.EXEC:nop                      43234709                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.811577                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    164032675                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   41211382                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 494218268                       # num instructions consuming a value
-system.cpu.iew.WB:count                     596241723                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.805354                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 492720055                       # num instructions consuming a value
+system.cpu.iew.WB:count                     595983189                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.807592                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 398020536                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.758758                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      597367655                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              4601660                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 2251946                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             127252956                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 28                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           3156398                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             43259984                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           665052109                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             122923051                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6371334                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             599454333                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                   2449                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                 397916939                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.801893                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      597091543                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              4603878                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 1505457                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             126939472                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 29                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           3143406                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             43126164                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           663744184                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             122821293                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6299898                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             599186314                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                   2121                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 33854                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               10007520                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 83713                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 28444                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                9844039                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 43665                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked          175                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads         5470953                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        10609                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked          720                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads         7235686                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        12544                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        93535                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         5935                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     12203446                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      3447461                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          93535                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       944573                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        3657087                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.668232                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.668232                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation        71476                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads         5929                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     11889962                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      3313641                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          71476                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       943110                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        3660768                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.709889                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.709889                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       438988101     72.46%     72.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult           6710      0.00%     72.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       438748901     72.46%     72.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult           6682      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     72.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd            30      0.00%     72.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd            29      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCmp             5      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCvt             5      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatMult            4      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     72.46% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     72.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      124874272     20.61%     93.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      41956540      6.93%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      124774485     20.61%     93.07% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      41956101      6.93%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        605825667                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               6927509                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.011435                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        605486212                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               7206090                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.011901                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu           5320205     76.80%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult               51      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     76.80% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          1245764     17.98%     94.78% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          361489      5.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu           5226098     72.52%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult               48      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     72.52% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          1579159     21.91%     94.44% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          400785      5.56%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    337425275                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.795437                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.663310                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    330660336                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.831143                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.672265                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      95395357     28.27%     28.27% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      68329461     20.25%     48.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      80056631     23.73%     72.25% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      36910615     10.94%     83.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      31840128      9.44%     92.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      12299933      3.65%     96.27% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      10951663      3.25%     99.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1050952      0.31%     99.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        590535      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      90539952     27.38%     27.38% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      66701453     20.17%     47.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      79600053     24.07%     71.63% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      36541170     11.05%     82.68% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      31317153      9.47%     92.15% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      13281184      4.02%     96.17% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6      11041150      3.34%     99.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       1066057      0.32%     99.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        572164      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    337425275                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.787028                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                  621764526                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 605825667                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  28                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        54809333                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             18475                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             11                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     31050369                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total    330660336                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.830624                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                  620509446                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 605486212                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  29                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        53535562                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             17232                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     29599324                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                65743973                       # ITB accesses
+system.cpu.itb.fetch_accesses                65649312                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    65743933                       # ITB hits
-system.cpu.itb.fetch_misses                        40                       # ITB misses
+system.cpu.itb.fetch_hits                    65649275                       # ITB hits
+system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -343,107 +343,98 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_acv                            0                       # DTB write access violations
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          256831                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               12642                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   8367822000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.950777                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            244189                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7606267000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.950777                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       244189                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            219184                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                183819                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1213040500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.161348                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               35365                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1096881500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.161348                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          35365                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          79334                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   2708405000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            79334                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2461697500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        79334                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          336082                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              336082                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5312.500000                       # average number of cycles each access was blocked
+system.cpu.l2cache.ReadExReq_accesses          256918                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits              197081                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2065711500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.232903                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             59837                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1879254000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.232903                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        59837                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            219092                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                186176                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1131972500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.150238                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               32916                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1021003500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.150238                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          32916                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          423151                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              423151                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5261.194030                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.798768                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs               72                       # number of cycles access was blocked
+system.cpu.l2cache.avg_refs                  5.283534                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs               67                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs       382500                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs       352500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             476015                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34271.956402                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 196461                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9580862500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.587280                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               279554                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses             476010                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34475.262256                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 383257                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     3197684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.194855                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                92753                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   8703148500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.587280                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          279554                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   2900257500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.194855                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           92753                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.052597                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.448200                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1723.488326                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14686.601231                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            476015                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34271.956402                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.052815                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.488399                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1730.637326                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16003.856484                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            476010                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34475.262256                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                196461                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9580862500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.587280                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              279554                       # number of overall misses
+system.cpu.l2cache.overall_hits                383257                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3197684000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.194855                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               92753                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   8703148500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.587280                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         279554                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   2900257500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.194855                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          92753                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 84626                       # number of replacements
-system.cpu.l2cache.sampled_refs                100342                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 74446                       # number of replacements
+system.cpu.l2cache.sampled_refs                 90349                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16410.089557                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  381176                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17734.493810                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  477362                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   62683                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          23861424                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         18454491                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            127252956                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            43259984                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                        339012994                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         14846495                       # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks                   59324                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          22261692                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         15435128                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            126939472                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            43126164                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                        330753974                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         12738848                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      463854889                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents        36228613                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         153406470                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1884931                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             97                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      897942713                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       681539497                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    519842559                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          115704820                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        10007520                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       43459223                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          55987670                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles          747                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts           33                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           87364721                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           33                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                           36935                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents        34708853                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         151708807                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents         618719                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents             82                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      896183749                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       680208714                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    518824645                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          115765657                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         9844039                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       40602289                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          54969756                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles          696                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts           32                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           79641546                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts           31                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                            3516                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 850a6530b..028c210bb 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index d9a9a6b92..9cd4e92a6 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:59:22
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:13:16
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -46,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 777351681000 because target called exit()
+Exiting @ tick 765623032000 because target called exit()
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index c92f137ce..ff829944e 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1386497                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206712                       # Number of bytes of host memory used
-host_seconds                                   434.08                       # Real time elapsed on the host
-host_tick_rate                             1790782589                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1603392                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192888                       # Number of bytes of host memory used
+host_seconds                                   375.37                       # Real time elapsed on the host
+host_tick_rate                             2039675547                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   601856964                       # Number of instructions simulated
-sim_seconds                                  0.777352                       # Number of seconds simulated
-sim_ticks                                777351681000                       # Number of ticks simulated
+sim_seconds                                  0.765623                       # Number of seconds simulated
+sim_ticks                                765623032000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              114312810                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4227398000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     4126262000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001757                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               201232                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3623702000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   3522566000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              39124493                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   17781358000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.008284                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              326828                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  16800874000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.008284                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         326828                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              39197158                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.006442                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              254163                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         254163                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 41678.513805                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               153437303                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     22008756000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003430                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                528060                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 22414.479737                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               153509968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002958                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                455395                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  20424576000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003430                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           528060                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           455395                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999560                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.197079                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.170317                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 41678.513805                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22414.479737                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              153437303                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    22008756000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003430                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               528060                       # number of overall misses
+system.cpu.dcache.overall_hits              153509968                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    10207442000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002958                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               455395                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  20424576000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003430                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          528060                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          455395                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 451299                       # number of replacements
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.197079                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.170317                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              578599000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   325740                       # number of writebacks
+system.cpu.dcache.warmup_cycle              578392000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   408190                       # number of writebacks
 system.cpu.dtb.data_accesses                153970296                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    153965363                       # DTB hits
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              795                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.328737                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            673.252668                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            673.337154                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     24                       # number of replacements
 system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                673.252668                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                673.337154                       # Cycle average of tags in use
 system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,37 +164,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses          254163                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               12405                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  12571416000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.951193                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            241758                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9670320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.951193                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       241758                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              194094                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.236340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             60069                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        60069                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            202027                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                167657                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1787240000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.170126                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               34370                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1374800000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.170126                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          34370                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          72665                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   3778580000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            72665                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2906600000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        72665                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          325740                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              325740                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                170065                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1662024000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.158207                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31962                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1278480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.158207                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31962                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              408190                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.553777                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.973210                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             456190                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 180062                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    14358656000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.605292                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               276128                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 364159                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4785612000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.201738                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                92031                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  11045120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.605292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          276128                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3681240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.201738                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           92031                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.052155                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.448358                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1709.012624                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14691.802112                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.052565                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.491366                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1722.436058                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16101.078831                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                180062                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   14358656000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.605292                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              276128                       # number of overall misses
+system.cpu.l2cache.overall_hits                364159                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4785612000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.201738                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               92031                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  11045120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.605292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         276128                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3681240000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.201738                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          92031                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 83906                       # number of replacements
-system.cpu.l2cache.sampled_refs                 99616                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 73734                       # number of replacements
+system.cpu.l2cache.sampled_refs                 89622                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16400.814735                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  354013                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17823.514890                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  445709                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   62672                       # number of writebacks
+system.cpu.l2cache.writebacks                   59341                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1554703362                       # number of cpu cycles simulated
+system.cpu.numCycles                       1531246064                       # number of cpu cycles simulated
 system.cpu.num_insts                        601856964                       # Number of instructions executed
 system.cpu.num_refs                         154866966                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index 4bef17201..19272883f 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index b26d693cf..107f995a8 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:54:54
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:05:18
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -45,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 807517408000 because target called exit()
+Exiting @ tick 796759936000 because target called exit()
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 4b4cf244a..11f65fd19 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1492183                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211112                       # Number of bytes of host memory used
-host_seconds                                   401.17                       # Real time elapsed on the host
-host_tick_rate                             2012902303                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1338185                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196956                       # Number of bytes of host memory used
+host_seconds                                   447.34                       # Real time elapsed on the host
+host_tick_rate                             1781116972                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   598619824                       # Number of instructions simulated
-sim_seconds                                  0.807517                       # Number of seconds simulated
-sim_ticks                                807517408000                       # Number of ticks simulated
+sim_seconds                                  0.796760                       # Number of seconds simulated
+sim_ticks                                796759936000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          147793610                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              147603767                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4006716000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     3956862000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001285                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               189843                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3437187000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   3387333000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001285                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          189843                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          69418858                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              69111608                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   16690534000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.004426                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              307250                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  15768784000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.004426                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         307250                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              69171110                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5180170000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 495.382394                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           217212468                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 41636.575047                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               216715375                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     20697250000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002289                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                497093                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 22578.791611                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               216774877                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9880276000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002015                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                437591                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  19205971000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002289                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           497093                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   8567503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002015                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           437591                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999572                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.246847                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.999566                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.223177                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          217212468                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 41636.575047                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22578.791611                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              216715375                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    20697250000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002289                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               497093                       # number of overall misses
+system.cpu.dcache.overall_hits              216774877                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9880276000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002015                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               437591                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  19205971000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002289                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          497093                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   8567503000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002015                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          437591                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 433495                       # number of replacements
 system.cpu.dcache.sampled_refs                 437591                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.246847                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.223177                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                216774877                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              537003000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   305501                       # number of writebacks
+system.cpu.dcache.writebacks                   392389                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses              643                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.282055                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            577.648910                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.282094                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            577.728453                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          570070553                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     12                       # number of replacements
 system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                577.648910                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                577.728453                       # Cycle average of tags in use
 system.cpu.icache.total_refs                570069910                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses          247748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               12273                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  12244700000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.950462                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            235475                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9419000000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.950462                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       235475                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              189297                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3039452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.235929                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             58451                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            190486                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                157753                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1702116000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.171839                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32733                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1309320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.171839                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32733                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          59502                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   3094104000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            59502                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2380080000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        59502                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          305501                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              305501                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                158940                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1640392000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.165608                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31546                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1261840000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165608                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31546                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          392389                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              392389                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.379196                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.718118                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             438234                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 170026                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    13946816000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.612020                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               268208                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 348237                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4679844000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.205363                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                89997                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  10728320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.612020                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          268208                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3599880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.205363                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           89997                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.050080                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.453180                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1641.035711                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14849.786647                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.053819                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.492601                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1763.554655                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16141.554862                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            438234                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                170026                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   13946816000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.612020                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              268208                       # number of overall misses
+system.cpu.l2cache.overall_hits                348237                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4679844000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.205363                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               89997                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  10728320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.612020                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         268208                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3599880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.205363                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          89997                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 80841                       # number of replacements
-system.cpu.l2cache.sampled_refs                 96272                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 71809                       # number of replacements
+system.cpu.l2cache.sampled_refs                 87292                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16490.822357                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  325322                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17905.109517                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  411854                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   60805                       # number of writebacks
+system.cpu.l2cache.writebacks                   57886                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1615034816                       # number of cpu cycles simulated
+system.cpu.numCycles                       1593519872                       # number of cpu cycles simulated
 system.cpu.num_insts                        598619824                       # Number of instructions executed
 system.cpu.num_refs                         219174038                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 659cb8ca7..5d6f66b52 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index d11cb55dd..b4e773530 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:05:09
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:20:33
+M5 executing on phenom
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -45,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1088441503500 because target called exit()
+Exiting @ tick 1095331467500 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 8e3cfada7..68e9f863d 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,423 +1,414 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  76473                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 212472                       # Number of bytes of host memory used
-host_seconds                                 18380.70                       # Real time elapsed on the host
-host_tick_rate                               59216546                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 138841                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 198176                       # Number of bytes of host memory used
+host_seconds                                 10123.96                       # Real time elapsed on the host
+host_tick_rate                              108192045                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1405618369                       # Number of instructions simulated
-sim_seconds                                  1.088442                       # Number of seconds simulated
-sim_ticks                                1088441503500                       # Number of ticks simulated
+sim_insts                                  1405618374                       # Number of instructions simulated
+sim_seconds                                  1.095331                       # Number of seconds simulated
+sim_ticks                                1095331467500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                173420048                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             194153919                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                175591574                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             198504175                       # Number of BTB lookups
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           81907161                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          251603669                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                251603669                       # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect           83489596                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          252577407                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                252577407                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               86248929                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           8072747                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events           9068364                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1941955406                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.767030                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.200667                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples   1951658061                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.763216                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.203742                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0   1072656731     55.24%     55.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    568585470     29.28%     84.51% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    118066725      6.08%     90.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3    122346784      6.30%     96.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     28028862      1.44%     98.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      8610798      0.44%     98.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     11084197      0.57%     99.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      4503092      0.23%     99.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      8072747      0.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0   1079992719     55.34%     55.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    573544089     29.39%     84.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2    118996755      6.10%     90.82% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3    118578034      6.08%     96.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     27958213      1.43%     98.33% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      7829070      0.40%     98.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     11095017      0.57%     99.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      4595800      0.24%     99.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      9068364      0.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1941955406                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                1489537512                       # Number of instructions committed
-system.cpu.commit.COM:loads                 402517247                       # Number of loads committed
+system.cpu.commit.COM:committed_per_cycle::total   1951658061                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                1489537517                       # Number of instructions committed
+system.cpu.commit.COM:loads                 402517252                       # Number of loads committed
 system.cpu.commit.COM:membars                   51356                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                  569375203                       # Number of memory references committed
+system.cpu.commit.COM:refs                  569375208                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          81907161                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts     1489537512                       # The number of committed instructions
+system.cpu.commit.branchMispredicts          83489596                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts     1489537517                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts      1348785802                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                  1405618369                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1405618369                       # Number of Instructions Simulated
-system.cpu.cpi                               1.548701                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.548701                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses          421715823                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6923.398779                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              420813257                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12864854000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002140                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               902566                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            664404                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1648890500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000565                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses          238162                       # number of ReadReq MSHR misses
+system.cpu.commit.commitSquashedInsts      1344365389                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                  1405618374                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1405618374                       # Number of Instructions Simulated
+system.cpu.cpi                               1.558505                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.558505                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses          428071377                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6644.344451                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              427202678                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    12103469000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.002029                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               868699                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            619015                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   1658986500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000583                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          249684                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                   1308                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency         684500                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.013575                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                   18                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       630500                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.013575                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses              18                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency         266500                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency       245500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         166856630                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             164663038                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   80123447685                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.013147                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             2193592                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1850133                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  12044158308                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002058                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         343459                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             165064790                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   25958081664                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.010739                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1791840                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1512123                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   3237699799                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001676                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         279717                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                1140.778331                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                1118.737886                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           588572453                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30033.448450                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               585476295                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     92988301685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005260                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               3096158                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2514537                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  13693048808                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000988                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           581621                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           594928007                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 14305.954795                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9249.484415                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               592267468                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     38061550664                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.004472                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2660539                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2131138                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   4896686299                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000890                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           529401                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999896                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4095.574913                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          588572453                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30033.448450                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.999897                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.577700                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          594928007                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 14305.954795                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9249.484415                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              585476295                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    92988301685                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005260                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              3096158                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2514537                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  13693048808                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000988                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          581621                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              592267468                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    38061550664                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.004472                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2660539                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2131138                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   4896686299                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000890                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          529401                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 509328                       # number of replacements
-system.cpu.dcache.sampled_refs                 513424                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 525312                       # number of replacements
+system.cpu.dcache.sampled_refs                 529408                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.574913                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                585702974                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              165969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   343309                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles      421597556                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts      3393767574                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         753336946                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          764050676                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       233579864                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles        2970228                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                   251603669                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 350205998                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                    1175621134                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes              10022642                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     3685217760                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                87763558                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.115580                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          350205998                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          173420048                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.692887                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         2175535270                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.693936                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.844478                       # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse               4095.577700                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                592268787                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              165936000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   467492                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles      419165001                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts      3408944329                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         761736999                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          767859019                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles       238675861                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles        2897042                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                   252577407                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 355041427                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                    1184621367                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes              11557522                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     3696750718                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                90055290                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.115297                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          355041427                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          175591574                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.687503                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples         2190333922                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.687757                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.837142                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1350120177     62.06%     62.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                247723459     11.39%     73.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 78876862      3.63%     77.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 36715633      1.69%     78.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 82505940      3.79%     82.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 39095379      1.80%     84.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 30113044      1.38%     85.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 19663449      0.90%     86.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                290721327     13.36%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1360754025     62.13%     62.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                248782776     11.36%     73.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 79015111      3.61%     77.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 36736924      1.68%     78.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 85275355      3.89%     82.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 39319900      1.80%     84.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 30979848      1.41%     85.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 19612924      0.90%     86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                289857059     13.23%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           2175535270                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses          350205998                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33274.163131                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              350203877                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       70574500                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total           2190333922                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses          355041427                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33183.081998                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              355039305                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       70414500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 2121                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               740                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     48047500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                 2122                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               746                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     47881500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            1381                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses            1376                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               253770.925362                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               258210.403636                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           350205998                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33274.163131                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               350203877                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        70574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses           355041427                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33183.081998                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               355039305                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        70414500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  2121                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                740                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     48047500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                  2122                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                746                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     47881500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             1381                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses             1376                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.517204                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1059.233334                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          350205998                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33274.163131                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.517160                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1059.143452                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          355041427                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33183.081998                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34797.601744                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              350203877                       # number of overall hits
-system.cpu.icache.overall_miss_latency       70574500                       # number of overall miss cycles
+system.cpu.icache.overall_hits              355039305                       # number of overall hits
+system.cpu.icache.overall_miss_latency       70414500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 2121                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               740                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     48047500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                 2122                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               746                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     47881500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            1381                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses            1376                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                    223                       # number of replacements
-system.cpu.icache.sampled_refs                   1380                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                    218                       # number of replacements
+system.cpu.icache.sampled_refs                   1375                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1059.233334                       # Cycle average of tags in use
-system.cpu.icache.total_refs                350203877                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1059.143452                       # Cycle average of tags in use
+system.cpu.icache.total_refs                355039305                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1347738                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                126526916                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     340982559                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.865733                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    746184493                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  208199925                       # Number of stores executed
+system.cpu.idleCycles                          329014                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                129329311                       # Number of branches executed
+system.cpu.iew.EXEC:nop                     343977069                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.860181                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    750434371                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  206174463                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1479878942                       # num instructions consuming a value
-system.cpu.iew.WB:count                    1850747692                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.963175                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                1480496045                       # num instructions consuming a value
+system.cpu.iew.WB:count                    1847584929                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.961963                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1425382580                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.850182                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     1860799390                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             88298258                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 3065589                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             732363888                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts           21345183                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          16501703                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            296834010                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2838380214                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             537984568                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          98702938                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            1884599663                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  42681                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                1424182878                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.843391                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     1859595547                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             91828645                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 2291655                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             731683017                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts           21329829                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts          16631995                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            299730608                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          2833977471                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             544259908                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          92682608                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            1884367319                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  43246                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 10075                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              233579864                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 76418                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  5071                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              238675861                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 70086                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked         3315                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads       116246268                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        24120                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked        28836                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads       116166112                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        85848                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation      6177679                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads           20                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    329846641                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores    129976054                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        6177679                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      2822462                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       85475796                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.645702                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.645702                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation      6831445                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            6                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    329165765                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores    132872652                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents        6831445                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      2781524                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       89047121                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.641641                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.641641                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1178510091     59.42%     59.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     59.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     59.42% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2995561      0.15%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     59.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      574193114     28.95%     88.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     227603835     11.48%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu      1175590605     59.46%     59.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     59.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2994259      0.15%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     59.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      570634170     28.86%     88.48% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite     227830893     11.52%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       1983302601                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               6030045                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.003040                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total       1977049927                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               4131140                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.002090                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            148667      2.47%      2.47% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      2.47% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      2.47% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd          233339      3.87%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      6.34% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          5333431     88.45%     94.78% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          314608      5.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu            148870      3.60%      3.60% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      3.60% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      3.60% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd          222262      5.38%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      8.98% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          3423281     82.87%     91.85% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          336727      8.15%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   2175535270                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.911639                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.163576                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples   2190333922                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.902625                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.145189                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0    1067990413     49.09%     49.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     580044793     26.66%     75.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     292279315     13.43%     89.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     158370905      7.28%     96.47% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      51349615      2.36%     98.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      15864540      0.73%     99.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       8721161      0.40%     99.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        777887      0.04%     99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        136641      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0    1077130624     49.18%     49.18% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     581443700     26.55%     75.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     301967857     13.79%     89.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3     159877963      7.30%     96.81% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      45264546      2.07%     98.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      18451049      0.84%     99.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       4794612      0.22%     99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       1273045      0.06%     99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        130526      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   2175535270                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.911075                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                 2475761446                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                1983302601                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded            21636209                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined      1050320205                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           3387342                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved       19392538                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined   1256970263                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses          275262                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               11754                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   9040806000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.957299                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            263508                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   8213610000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.957299                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       263508                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            239543                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                204890                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1181858000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.144663                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               34653                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1074330000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.144663                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          34653                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          68215                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   2333844500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            68215                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2116155000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        68215                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          343309                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              343309                       # number of Writeback hits
+system.cpu.iq.ISSUE:issued_per_cycle::total   2190333922                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.902489                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                 2468355699                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                1977049927                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded            21644703                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined      1031033219                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            637277                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved       19401032                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined   1242826340                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses          279724                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits              218618                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2110047500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.218451                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             61106                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1917896000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.218451                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        61106                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            251060                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                217208                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1153541000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.134836                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               33852                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1049484000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.134836                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          33852                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          467492                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              467492                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.105608                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.866131                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             514805                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34285.718119                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 216644                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    10222664000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.579173                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               298161                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses             530784                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34368.757767                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 435826                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     3263588500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.178901                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                94958                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   9287940000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.579173                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          298161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   2967380000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.178901                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           94958                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.057090                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.444973                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1870.709103                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14580.888860                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            514805                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34285.718119                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.061469                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.477467                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2014.215255                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15645.646003                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            530784                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34368.757767                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                216644                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   10222664000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.579173                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              298161                       # number of overall misses
+system.cpu.l2cache.overall_hits                435826                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3263588500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.178901                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               94958                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   9287940000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.579173                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         298161                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   2967380000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.178901                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          94958                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 83969                       # number of replacements
-system.cpu.l2cache.sampled_refs                 99434                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 76745                       # number of replacements
+system.cpu.l2cache.sampled_refs                 92262                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16451.597962                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  408237                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17659.861257                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  541221                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   61561                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         445088392                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        142143895                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            732363888                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           296834010                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                       2176883008                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         18665128                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps     1244779258                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents          724                       # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents           28925                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         816745640                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       24395596                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents              7                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     4856285750                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      3051371057                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2392375919                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          700064958                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       233579864                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       34053219                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps        1147596661                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles    372426461                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts     21718962                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts          176891245                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts     21553313                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                           41709                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.l2cache.writebacks                   59365                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         443698156                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        136383139                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            731683017                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           299730608                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                       2190662936                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         17189054                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps     1244779268                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:FullRegisterEvents          463                       # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents           34257                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         824291881                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       24214806                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents              8                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     4869886562                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      3060544953                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   2396042530                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          704670101                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles       238675861                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       33809858                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps        1151263262                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles    371697167                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts     21697179                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts          175779479                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts     21533408                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                            8581                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 9514e3ea7..9772b8626 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 833f1cfc2..78e3d8264 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:04:04
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:28:00
+M5 executing on phenom
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -45,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2075400743000 because target called exit()
+Exiting @ tick 2064258667000 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 736d779d0..04e7c144d 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1385286                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211532                       # Number of bytes of host memory used
-host_seconds                                  1075.25                       # Real time elapsed on the host
-host_tick_rate                             1930162951                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1333935                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197236                       # Number of bytes of host memory used
+host_seconds                                  1116.64                       # Real time elapsed on the host
+host_tick_rate                             1848636408                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
-sim_seconds                                  2.075401                       # Number of seconds simulated
-sim_ticks                                2075400743000                       # Number of ticks simulated
+sim_seconds                                  2.064259                       # Number of seconds simulated
+sim_ticks                                2064258667000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          402512844                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              402319358                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4065698000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     4019834000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000481                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               193486                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3485240000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   3439376000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000481                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          193486                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                   1308                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency        1008000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.013575                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                   18                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       954000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.013575                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses              18                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency         392000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency       371000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             166528617                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   17311026000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.001907                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              318199                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  16356429000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001907                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         318199                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             166587088                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    6156948000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.001557                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              259728                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5377764000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001557                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         259728                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
@@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           569359660                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 41777.116781                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               568847975                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     21376724000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000899                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                511685                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 22454.694692                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               568906446                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     10176782000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000796                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                453214                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  19841669000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000899                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           511685                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   8817140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000796                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           453214                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999812                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4095.231029                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.999811                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4095.226955                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 41777.116781                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22454.694692                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              568847975                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    21376724000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000899                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               511685                       # number of overall misses
+system.cpu.dcache.overall_hits              568906446                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    10176782000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000796                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               453214                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  19841669000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000899                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          511685                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   8817140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000796                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          453214                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 449125                       # number of replacements
 system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.231029                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.226955                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              567036000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   316439                       # number of writebacks
+system.cpu.dcache.warmup_cycle              566994000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   407009                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1485113012                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55848.238482                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482                       # average ReadReq mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses             1107                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.442593                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            906.429761                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.442603                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            906.450625                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
@@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                    118                       # number of replacements
 system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                906.429761                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                906.450625                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -142,37 +142,28 @@ system.cpu.idle_fraction                            0                       # Pe
 system.cpu.l2cache.ReadExReq_accesses          259735                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               12098                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  12877124000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.953422                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            247637                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9905480000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.953422                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       247637                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              199710                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3121300000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.231101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             60025                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2401000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.231101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        60025                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            194593                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                161183                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1737320000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.171692                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               33410                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1336400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.171692                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          33410                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          58482                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   3040960000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            58482                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2339280000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        58482                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          316439                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              316439                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                162275                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1680536000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.166080                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               32318                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1292720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.166080                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          32318                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          407009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              407009                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.448937                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.765989                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             454328                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 173281                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    14614444000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.618599                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               281047                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 361985                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4801836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.203252                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                92343                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  11241880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.618599                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          281047                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3693720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.203252                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           92343                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.052996                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.447533                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1736.572582                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14664.762880                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.057187                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.483685                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1873.919591                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15849.385934                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                173281                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   14614444000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.618599                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              281047                       # number of overall misses
+system.cpu.l2cache.overall_hits                361985                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4801836000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.203252                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               92343                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  11241880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.618599                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         281047                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3693720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.203252                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          92343                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 82461                       # number of replacements
-system.cpu.l2cache.sampled_refs                 97909                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 74112                       # number of replacements
+system.cpu.l2cache.sampled_refs                 89611                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16401.335462                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  337682                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             17723.305524                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  427085                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   61551                       # number of writebacks
+system.cpu.l2cache.writebacks                   59035                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4150801486                       # number of cpu cycles simulated
+system.cpu.numCycles                       4128517334                       # number of cpu cycles simulated
 system.cpu.num_insts                       1489523295                       # Number of instructions executed
 system.cpu.num_refs                         569365767                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 1bbdb5a19..da2490100 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 5c6b0de63..d309b71a7 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:20:12
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:33:02
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:29:10
+M5 executing on phenom
 command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -46,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1814105620000 because target called exit()
+Exiting @ tick 1803258587000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index f79a1a362..f28dbcde3 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1308474                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210192                       # Number of bytes of host memory used
-host_seconds                                  1237.60                       # Real time elapsed on the host
-host_tick_rate                             1465826235                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1292356                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195556                       # Number of bytes of host memory used
+host_seconds                                  1253.03                       # Real time elapsed on the host
+host_tick_rate                             1439113315                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619366787                       # Number of instructions simulated
-sim_seconds                                  1.814106                       # Number of seconds simulated
-sim_ticks                                1814105620000                       # Number of ticks simulated
+sim_seconds                                  1.803259                       # Number of seconds simulated
+sim_ticks                                1803258587000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          419042125                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              418844799                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4107782000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     4043270000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000471                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               197326                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3515804000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   3451292000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000471                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          197326                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             187878126                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   16718464000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.001636                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              307931                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  15794671000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001636                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         307931                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             187941335                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5872734000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.001300                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              244722                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5138568000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.001300                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         244722                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                1372.670239                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           607228182                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 41219.114233                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               606722925                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     20826246000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000832                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                505257                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 22431.962140                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               606786134                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9916004000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000728                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                442048                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  19310475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000832                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           505257                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   8589860000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000728                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           442048                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.999732                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.903534                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.999731                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.896939                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          607228182                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 41219.114233                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22431.962140                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              606722925                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    20826246000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000832                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               505257                       # number of overall misses
+system.cpu.dcache.overall_hits              606786134                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9916004000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000728                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               442048                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  19310475000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000832                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          505257                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   8589860000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000728                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          442048                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 437952                       # number of replacements
 system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.903534                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.896939                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                606786134                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              778540000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   306200                       # number of writebacks
+system.cpu.dcache.writebacks                   396372                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1186516740                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              722                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.322353                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            660.178535                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.322357                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            660.186297                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1186516740                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      4                       # number of replacements
 system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                660.178535                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                660.186297                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1186516018                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -132,37 +132,28 @@ system.cpu.idle_fraction                            0                       # Pe
 system.cpu.l2cache.ReadExReq_accesses          244722                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               12516                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  12074712000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.948856                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            232206                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9288240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.948856                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       232206                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              186469                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3029156000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.238037                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             58253                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2330120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.238037                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        58253                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            198048                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                165297                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1703052000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.165369                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32751                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1310040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165369                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32751                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          63209                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   3286868000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            63209                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   2528360000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        63209                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          306200                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              306200                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                166833                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1623180000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.157613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31215                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1248600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31215                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          396372                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              396372                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.450731                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.873826                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             442770                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 177813                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    13777764000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.598408                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               264957                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 353302                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     4652336000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.202064                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                89468                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  10598280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.598408                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          264957                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3578720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.202064                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           89468                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.053631                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.452717                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1757.366037                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14834.623829                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.057043                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.494010                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1869.199731                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16187.723361                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            442770                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                177813                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   13777764000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.598408                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              264957                       # number of overall misses
+system.cpu.l2cache.overall_hits                353302                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    4652336000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.202064                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               89468                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  10598280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.598408                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         264957                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3578720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.202064                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          89468                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 81078                       # number of replacements
-system.cpu.l2cache.sampled_refs                 96612                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 71208                       # number of replacements
+system.cpu.l2cache.sampled_refs                 86793                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16591.989866                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  333382                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18056.923092                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  423014                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   61253                       # number of writebacks
+system.cpu.l2cache.writebacks                   58007                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3628211240                       # number of cpu cycles simulated
+system.cpu.numCycles                       3606517174                       # number of cpu cycles simulated
 system.cpu.num_insts                       1619366787                       # Number of instructions executed
 system.cpu.num_refs                         607228182                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 1430c935e..14fd768c1 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -661,7 +661,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -681,7 +681,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -807,7 +807,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 592fcc28f..87e8bb8fc 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,14 +5,14 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:16
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:17:04
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 125480500
-Exiting @ tick 1906675009500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 118370500
+Exiting @ tick 1900828642500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index a77677815..a900ae38f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,449 +1,449 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  96877                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 294552                       # Number of bytes of host memory used
-host_seconds                                   589.85                       # Real time elapsed on the host
-host_tick_rate                             3232468675                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 158375                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 283016                       # Number of bytes of host memory used
+host_seconds                                   359.78                       # Real time elapsed on the host
+host_tick_rate                             5283356726                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    57142904                       # Number of instructions simulated
-sim_seconds                                  1.906675                       # Number of seconds simulated
-sim_ticks                                1906675009500                       # Number of ticks simulated
+sim_insts                                    56979511                       # Number of instructions simulated
+sim_seconds                                  1.900829                       # Number of seconds simulated
+sim_ticks                                1900828642500                       # Number of ticks simulated
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits                 6037320                       # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups             11351967                       # Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect              27838                       # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect            689824                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted          10583458                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups                12665096                       # Number of BP lookups
-system.cpu0.BPredUnit.usedRAS                  889173                       # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches               7532122                       # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events           868474                       # number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits                 5876227                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups             11175399                       # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect              27772                       # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect            686228                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted          10431445                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups                12491766                       # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS                  881103                       # Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches               7527502                       # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events           920717                       # number cycles where commit BW limit reached
 system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples     85531488                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean     0.582160                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev     1.346009                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples     78591026                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean     0.633671                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev     1.400615                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0     64118131     74.96%     74.96% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1      9419985     11.01%     85.98% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2      5464530      6.39%     92.37% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3      2511151      2.94%     95.30% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4      1836761      2.15%     97.45% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5       609168      0.71%     98.16% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6       353146      0.41%     98.58% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7       350142      0.41%     98.98% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8       868474      1.02%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0     57312142     72.92%     72.92% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1      9330889     11.87%     84.80% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2      5427191      6.91%     91.70% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3      2440699      3.11%     94.81% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4      1862016      2.37%     97.18% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5       630346      0.80%     97.98% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6       341230      0.43%     98.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7       325796      0.41%     98.83% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8       920717      1.17%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total     85531488                       # Number of insts commited each cycle
-system.cpu0.commit.COM:count                 49793044                       # Number of instructions committed
-system.cpu0.commit.COM:loads                  8087035                       # Number of loads committed
-system.cpu0.commit.COM:membars                 188923                       # Number of memory barriers committed
-system.cpu0.commit.COM:refs                  13499415                       # Number of memory references committed
+system.cpu0.commit.COM:committed_per_cycle::total     78591026                       # Number of insts commited each cycle
+system.cpu0.commit.COM:count                 49800850                       # Number of instructions committed
+system.cpu0.commit.COM:loads                  8090667                       # Number of loads committed
+system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
+system.cpu0.commit.COM:refs                  13515444                       # Number of memory references committed
 system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts           656667                       # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts      49793044                       # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls         558254                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts        7909295                       # The number of squashed insts skipped by commit
-system.cpu0.committedInsts                   46950766                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total             46950766                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.557983                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.557983                       # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0       175325                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       175325                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13891.838160                       # average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts           653618                       # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts      49800850                       # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls         564747                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts        7272798                       # The number of squashed insts skipped by commit
+system.cpu0.committedInsts                   46939821                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             46939821                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.403302                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.403302                       # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0       178200                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       178200                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14347.227969                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10378.791946                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0       156714                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       156714                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    258541000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.106151                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        18611                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18611                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits         3711                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    154644000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084985                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10538.474362                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0       158864                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       158864                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    277418000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108507                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0        19336                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19336                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits         4339                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158045500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084158                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        14900                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0        8024582                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8024582                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 24823.193475                       # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses        14997                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0        8021076                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8021076                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.144269                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23777.445948                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.790910                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0            6693712                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6693712                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   33036443500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0      0.165849                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0          1330870                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1330870                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits           349277                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23339774500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122323                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0            6644033                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6644033                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   32707724000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0      0.171678                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0          1377043                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1377043                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits           391877                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23415219500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122822                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses         981593                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    922661000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0       183239                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       183239                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 47093.631014                       # average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses         985166                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920846500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0       185095                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       185095                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13168.588688                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 44096.203773                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0        165905                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       165905                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency    816321000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.094598                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0        17334                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        17334                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency    764319500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.094592                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10165.293795                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0        181453                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       181453                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency     47960000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.019676                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0         3642                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         3642                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37022000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.019676                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses        17333                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0       5213801                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5213801                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 48517.051427                       # average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses         3642                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0       5224623                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5224623                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 32385.164412                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53069.050136                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30570.974366                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0           3350446                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3350446                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency  90404490361                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0     0.357389                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0         1863355                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1863355                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits         1547991                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency  16736067927                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.060486                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0           3608317                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3608317                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency  52344335550                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0     0.309363                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0         1616306                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1616306                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits         1352902                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8052516932                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050416                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        315364                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1337193497                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  9713.605174                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  8.464502                       # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs           124903                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              6                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs   1213258427                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       129000                       # number of cycles access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses        263404                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320254998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8777.270227                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 21937.500000                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs                  8.502455                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs            83541                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              8                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs    733261932                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       175500                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        13238383                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0        13245699                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13238383                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 38645.034041                       # average overall miss latency
+system.cpu0.dcache.demand_accesses::total     13245699                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 28413.679644                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 30899.900634                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            10044158                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 25203.021402                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0            10252350                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10044158                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency   123440933861                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.241285                       # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total        10252350                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    85052059550                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0       0.225986                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           3194225                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0           2993349                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3194225                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits           1897268                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  40075842427                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.097969                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_misses::total       2993349                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits           1744779                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency  31467736432                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.094262                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1296957                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1248570                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.975170                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1                 -0.005787                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0           499.286946                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -2.962988                       # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0       13238383                       # number of overall (read+write) accesses
+system.cpu0.dcache.occ_%::0                  0.973042                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0           498.197480                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses::0       13245699                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13238383                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 38645.034041                       # average overall miss latency
+system.cpu0.dcache.overall_accesses::total     13245699                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 28413.679644                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 30899.900634                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 25203.021402                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           10044158                       # number of overall hits
+system.cpu0.dcache.overall_hits::0           10252350                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10044158                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency  123440933861                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.241285                       # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total       10252350                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   85052059550                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0      0.225986                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          3194225                       # number of overall misses
+system.cpu0.dcache.overall_misses::0          2993349                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3194225                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits          1897268                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  40075842427                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.097969                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_misses::total      2993349                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits          1744779                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency  31467736432                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.094262                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1296957                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2259854497                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses        1248570                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2241101498                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1243005                       # number of replacements
-system.cpu0.dcache.sampled_refs               1243517                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1246736                       # number of replacements
+system.cpu0.dcache.sampled_refs               1247248                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               497.305455                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                10525752                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               497.197481                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                10604670                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  379678                       # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles      40702182                       # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred         33733                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved       526303                       # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts       63705520                       # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles         32342676                       # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles          11446881                       # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles        1370864                       # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts        100557                       # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles       1039748                       # Number of cycles decode is unblocking
-system.cpu0.dtb.data_accesses                  867376                       # DTB accesses
-system.cpu0.dtb.data_acv                          796                       # DTB access violations
-system.cpu0.dtb.data_hits                    14352894                       # DTB hits
-system.cpu0.dtb.data_misses                     32526                       # DTB misses
+system.cpu0.dcache.writebacks                  721609                       # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles      34091757                       # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred         33333                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved       521194                       # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts       62604059                       # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles         32208044                       # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles          11309029                       # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles        1270122                       # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts        100597                       # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles        982195                       # Number of cycles decode is unblocking
+system.cpu0.dtb.data_accesses                  794086                       # DTB accesses
+system.cpu0.dtb.data_acv                          680                       # DTB access violations
+system.cpu0.dtb.data_hits                    14244186                       # DTB hits
+system.cpu0.dtb.data_misses                     32160                       # DTB misses
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  645773                       # DTB read accesses
-system.cpu0.dtb.read_acv                          589                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8766713                       # DTB read hits
-system.cpu0.dtb.read_misses                     26860                       # DTB read misses
-system.cpu0.dtb.write_accesses                 221603                       # DTB write accesses
-system.cpu0.dtb.write_acv                         207                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5586181                       # DTB write hits
-system.cpu0.dtb.write_misses                     5666                       # DTB write misses
-system.cpu0.fetch.Branches                   12665096                       # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines                  7900913                       # Number of cache lines fetched
-system.cpu0.fetch.Cycles                     20614864                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes               378846                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts                      65028610                       # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles                1156                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles                 811969                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate                 0.105455                       # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles           7900913                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches           6926493                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate                       0.541457                       # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples          86902352                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.748295                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.044395                       # Number of instructions fetched each cycle (Total)
+system.cpu0.dtb.read_accesses                  598785                       # DTB read accesses
+system.cpu0.dtb.read_acv                          509                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8659679                       # DTB read hits
+system.cpu0.dtb.read_misses                     26490                       # DTB read misses
+system.cpu0.dtb.write_accesses                 195301                       # DTB write accesses
+system.cpu0.dtb.write_acv                         171                       # DTB write access violations
+system.cpu0.dtb.write_hits                    5584507                       # DTB write hits
+system.cpu0.dtb.write_misses                     5670                       # DTB write misses
+system.cpu0.fetch.Branches                   12491766                       # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines                  7797156                       # Number of cache lines fetched
+system.cpu0.fetch.Cycles                     20279244                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes               375144                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts                      63684763                       # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles                 883                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles                 746145                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate                 0.110732                       # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles           7797156                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches           6757330                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate                       0.564528                       # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples          79861148                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.797444                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.100172                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                74220009     85.41%     85.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  901339      1.04%     86.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1804427      2.08%     88.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  827724      0.95%     89.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2764395      3.18%     92.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  592140      0.68%     93.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  693087      0.80%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  935405      1.08%     95.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4163826      4.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                67408745     84.41%     84.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  900507      1.13%     85.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1775612      2.22%     87.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  807193      1.01%     88.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2749132      3.44%     92.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  585022      0.73%     92.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  680161      0.85%     93.80% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  829359      1.04%     94.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4125417      5.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            86902352                       # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses::0        7900913                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7900913                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 15047.285683                       # average ReadReq miss latency
+system.cpu0.fetch.rateDist::total            79861148                       # Number of instructions fetched each cycle (Total)
+system.cpu0.icache.ReadReq_accesses::0        7797156                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7797156                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15068.131136                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12005.143233                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0            7053204                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7053204                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   12755719499                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0      0.107293                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           847709                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       847709                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits            37907                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency   9721789000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.102495                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.324658                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits::0            6939758                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6939758                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency   12919385500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate::0      0.109963                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0           857398                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       857398                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits            36516                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency   9864805500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105280                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         809802                       # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11235.849057                       # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_mshr_misses         820882                       # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11596.153846                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                  8.711370                       # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs               53                       # number of cycles access was blocked
+system.cpu0.icache.avg_refs                  8.455231                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs               52                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs       595500                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs       603000                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0         7900913                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::0         7797156                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7900913                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 15047.285683                       # average overall miss latency
+system.cpu0.icache.demand_accesses::total      7797156                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 15068.131136                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12005.143233                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0             7053204                       # number of demand (read+write) hits
+system.cpu0.icache.demand_avg_mshr_miss_latency 12017.324658                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits::0             6939758                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7053204                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    12755719499                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.107293                       # miss rate for demand accesses
+system.cpu0.icache.demand_hits::total         6939758                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency    12919385500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate::0       0.109963                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            847709                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::0            857398                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        847709                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits             37907                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency   9721789000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0     0.102495                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_misses::total        857398                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits             36516                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency   9864805500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate::0     0.105280                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          809802                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses          820882                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.995703                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0           509.799701                       # Average occupied blocks per context
-system.cpu0.icache.overall_accesses::0        7900913                       # number of overall (read+write) accesses
+system.cpu0.icache.occ_%::0                  0.995823                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0           509.861438                       # Average occupied blocks per context
+system.cpu0.icache.overall_accesses::0        7797156                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7900913                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 15047.285683                       # average overall miss latency
+system.cpu0.icache.overall_accesses::total      7797156                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 15068.131136                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12005.143233                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12017.324658                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0            7053204                       # number of overall hits
+system.cpu0.icache.overall_hits::0            6939758                       # number of overall hits
 system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7053204                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   12755719499                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.107293                       # miss rate for overall accesses
+system.cpu0.icache.overall_hits::total        6939758                       # number of overall hits
+system.cpu0.icache.overall_miss_latency   12919385500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate::0      0.109963                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           847709                       # number of overall misses
+system.cpu0.icache.overall_misses::0           857398                       # number of overall misses
 system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       847709                       # number of overall misses
-system.cpu0.icache.overall_mshr_hits            37907                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency   9721789000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0     0.102495                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_misses::total       857398                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits            36516                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency   9864805500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate::0     0.105280                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         809802                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses         820882                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                809144                       # number of replacements
-system.cpu0.icache.sampled_refs                809655                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                820254                       # number of replacements
+system.cpu0.icache.sampled_refs                820765                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               509.799701                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 7053204                       # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           25253244000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                       2                       # number of writebacks
-system.cpu0.idleCycles                       33196891                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches                 8125364                       # Number of branches executed
-system.cpu0.iew.EXEC:nop                      3226641                       # number of nop insts executed
-system.cpu0.iew.EXEC:rate                    0.422366                       # Inst execution rate
-system.cpu0.iew.EXEC:refs                    14615271                       # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores                   5604883                       # Number of stores executed
+system.cpu0.icache.tagsinuse               509.861438                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 6939758                       # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           24435354000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks                     108                       # number of writebacks
+system.cpu0.idleCycles                       32949400                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches                 8094203                       # Number of branches executed
+system.cpu0.iew.EXEC:nop                      3189422                       # number of nop insts executed
+system.cpu0.iew.EXEC:rate                    0.446630                       # Inst execution rate
+system.cpu0.iew.EXEC:refs                    14505244                       # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores                   5602935                       # Number of stores executed
 system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu0.iew.WB:consumers                 31032245                       # num instructions consuming a value
-system.cpu0.iew.WB:count                     50227097                       # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout                    0.763961                       # average fanout of values written-back
+system.cpu0.iew.WB:consumers                 31589475                       # num instructions consuming a value
+system.cpu0.iew.WB:count                     50006148                       # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout                    0.758030                       # average fanout of values written-back
 system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers                 23707433                       # num instructions producing a value
-system.cpu0.iew.WB:rate                      0.418213                       # insts written-back per cycle
-system.cpu0.iew.WB:sent                      50304093                       # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts              713455                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles                9315247                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts              9510497                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts           1499135                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts           880070                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts             5918886                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts           57821470                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts              9010388                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           501816                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts             50725864                       # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents                 38579                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers                 23945765                       # num instructions producing a value
+system.cpu0.iew.WB:rate                      0.443275                       # insts written-back per cycle
+system.cpu0.iew.WB:sent                      50087986                       # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts              712279                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles                9112948                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts              9340675                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts           1511795                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts           758903                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts             5843423                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts           57183881                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts              8902309                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           466602                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts             50384547                       # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents                 59804                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents                 5036                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles               1370864                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles               530507                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewLSQFullEvents                 6983                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles               1270122                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles               547925                       # Number of cycles IEW is unblocking
 system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked       262065                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads         407910                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses        13281                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked       121839                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads         411299                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses        11485                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation        40793                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads        18036                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads      1423462                       # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores       506506                       # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents         40793                       # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect       332881                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect        380574                       # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc                              0.390933                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.390933                       # IPC: Total IPC of All Threads
-system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3770      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35394718     69.09%     69.10% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult         55798      0.11%     69.21% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.21% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15086      0.03%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1884      0.00%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     69.24% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead       9327899     18.21%     87.45% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645566     11.02%     98.47% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess       782961      1.53%    100.00% # Type of FU issued
+system.cpu0.iew.lsq.thread.0.memOrderViolation        38596                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads        18609                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads      1250008                       # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores       418646                       # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents         38596                       # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect       332551                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        379728                       # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc                              0.416094                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.416094                       # IPC: Total IPC of All Threads
+system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3763      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35146664     69.12%     69.12% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntMult         56139      0.11%     69.23% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.23% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15323      0.03%     69.26% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.26% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     69.26% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     69.26% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1880      0.00%     69.27% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     69.27% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead       9202305     18.10%     87.36% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645893     11.10%     98.47% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779184      1.53%    100.00% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total        51227682                       # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt               363911                       # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate            0.007104                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:FU_type_0::total        50851151                       # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt               379787                       # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate            0.007469                       # FU busy rate (busy events/executed inst)
 system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu            39751     10.92%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     10.92% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead          236746     65.06%     75.98% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite          87414     24.02%    100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu            40748     10.73%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     10.73% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead          225975     59.50%     70.23% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite         113064     29.77%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples     86902352                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.589486                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.157706                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples     79861148                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.636745                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.207484                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0     61545337     70.82%     70.82% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1     12554046     14.45%     85.27% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2      5586431      6.43%     91.70% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3      3486187      4.01%     95.71% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4      2264793      2.61%     98.31% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5       945170      1.09%     99.40% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6       407098      0.47%     99.87% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7        91717      0.11%     99.98% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8        21573      0.02%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0     55051799     68.93%     68.93% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1     12151486     15.22%     84.15% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2      5444442      6.82%     90.97% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3      3407774      4.27%     95.23% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4      2222623      2.78%     98.02% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5       997342      1.25%     99.27% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6       433832      0.54%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7       107535      0.13%     99.94% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8        44315      0.06%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total     86902352                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate                    0.426545                       # Inst issue rate
-system.cpu0.iq.iqInstsAdded                  52886391                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued                 51227682                       # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded            1708438                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined        7322246                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued            33660                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved       1150184                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined      3910877                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.ISSUE:issued_per_cycle::total     79861148                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate                    0.450766                       # Inst issue rate
+system.cpu0.iq.iqInstsAdded                  52272510                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued                 50851151                       # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded            1721949                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined        6732996                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued            24094                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved       1157202                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined      3425901                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_hits                           0                       # DTB hits
 system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                 999568                       # ITB accesses
-system.cpu0.itb.fetch_acv                         893                       # ITB acv
-system.cpu0.itb.fetch_hits                     968847                       # ITB hits
-system.cpu0.itb.fetch_misses                    30721                       # ITB misses
+system.cpu0.itb.fetch_accesses                 952090                       # ITB accesses
+system.cpu0.itb.fetch_acv                         738                       # ITB acv
+system.cpu0.itb.fetch_hits                     923140                       # ITB hits
+system.cpu0.itb.fetch_misses                    28950                       # ITB misses
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -453,550 +453,550 @@ system.cpu0.itb.write_acv                           0                       # DT
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  393      0.25%      0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.25% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.25% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3319      2.08%      2.33% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.03%      2.36% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.36% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               144424     90.42%     92.78% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6390      4.00%     96.78% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.79% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.79% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.79% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.79% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4592      2.87%     99.67% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 391      0.24%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  351      0.22%      0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.22% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3287      2.03%      2.25% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      43      0.03%      2.27% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               147044     90.75%     93.03% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6369      3.93%     96.96% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.96% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.96% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     7      0.00%     96.96% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4450      2.75%     99.71% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 330      0.20%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                159723                       # number of callpals executed
+system.cpu0.kern.callpal::total                162036                       # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    175260                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6689                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0                   61186     40.39%     40.39% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    239      0.16%     40.55% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1930      1.27%     41.82% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    300      0.20%     42.02% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  87830     57.98%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              151485                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    60407     49.12%     49.12% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     239      0.19%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1930      1.57%     50.88% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     300      0.24%     51.13% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   60108     48.87%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               122984                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1866417310500     97.89%     97.89% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               97564500      0.01%     97.89% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              399841000      0.02%     97.91% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              136212500      0.01%     97.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            39623165500      2.08%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1906674094000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.987268                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.hwrei                    176105                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6623                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count::0                   62137     40.37%     40.37% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    238      0.15%     40.53% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1925      1.25%     41.78% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    254      0.17%     41.94% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  89358     58.06%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              153912                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    61267     49.13%     49.13% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     238      0.19%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1925      1.54%     50.87% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     254      0.20%     51.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   61013     48.93%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               124697                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1862678817000     97.99%     97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               96273000      0.01%     98.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              398546000      0.02%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              103367000      0.01%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            37550788000      1.98%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1900827791000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.985999                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684368                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1353                      
-system.cpu0.kern.mode_good::user                 1354                      
+system.cpu0.kern.ipl_used::31                0.682793                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel               1171                      
+system.cpu0.kern.mode_good::user                 1172                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch::kernel             7157                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1354                       # number of protection mode switches
+system.cpu0.kern.mode_switch::kernel             6890                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1172                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.189046                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.169956                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1904400738500     99.88%     99.88% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2273347500      0.12%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1898857065000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1970718000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3320                       # number of times the context was actually changed
-system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
-system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
-system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
-system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
-system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
-system.cpu0.memDep0.conflictingLoads          2539862                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2208172                       # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads             9510497                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5918886                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles                       120099243                       # number of cpu cycles simulated
-system.cpu0.rename.RENAME:BlockCycles        13446049                       # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps      34012953                       # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents        1022261                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles         33782009                       # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents       1807708                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents         16757                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups      73652966                       # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts       60220724                       # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands     40595001                       # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles          11156910                       # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles        1370864                       # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles       4406747                       # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps          6582046                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles     22739771                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts      1403717                       # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts          10900390                       # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts       213877                       # count of temporary serializing insts renamed
-system.cpu0.timesIdled                        1182515                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.kern.swap_context                    3288                       # number of times the context was actually changed
+system.cpu0.kern.syscall::2                         6      2.99%      2.99% # number of syscalls executed
+system.cpu0.kern.syscall::3                        17      8.46%     11.44% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.49%     12.94% # number of syscalls executed
+system.cpu0.kern.syscall::6                        27     13.43%     26.37% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.50%     26.87% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.48%     31.34% # number of syscalls executed
+system.cpu0.kern.syscall::19                        6      2.99%     34.33% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      1.99%     36.32% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.50%     36.82% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.49%     38.31% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.48%     41.79% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      1.00%     42.79% # number of syscalls executed
+system.cpu0.kern.syscall::45                       36     17.91%     60.70% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.49%     62.19% # number of syscalls executed
+system.cpu0.kern.syscall::48                        7      3.48%     65.67% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.48%     70.15% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.50%     70.65% # number of syscalls executed
+system.cpu0.kern.syscall::59                        5      2.49%     73.13% # number of syscalls executed
+system.cpu0.kern.syscall::71                       27     13.43%     86.57% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.49%     88.06% # number of syscalls executed
+system.cpu0.kern.syscall::74                        7      3.48%     91.54% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.50%     92.04% # number of syscalls executed
+system.cpu0.kern.syscall::90                        1      0.50%     92.54% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.48%     96.02% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      1.00%     97.01% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      1.00%     98.01% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.50%     98.51% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.50%     99.00% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      1.00%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   201                       # number of syscalls executed
+system.cpu0.memDep0.conflictingLoads          2328642                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1937858                       # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads             9340675                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5843423                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.numCycles                       112810548                       # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles        12992019                       # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps      33999562                       # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents        1006246                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles         33622049                       # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents       1438466                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents         43293                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups      72562175                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts       59339637                       # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands     39991159                       # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles          11032673                       # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles        1270122                       # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles       4054916                       # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps          5991595                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles     16889367                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts      1393634                       # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts          10149085                       # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts       207632                       # count of temporary serializing insts renamed
+system.cpu0.timesIdled                        1187372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits                 1168869                       # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups              2724358                       # Number of BTB lookups
-system.cpu1.BPredUnit.RASInCorrect               8216                       # Number of incorrect RAS predictions.
-system.cpu1.BPredUnit.condIncorrect            170435                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted           2536443                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups                 3058879                       # Number of BP lookups
-system.cpu1.BPredUnit.usedRAS                  214059                       # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches               1536055                       # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events           205800                       # number cycles where commit BW limit reached
+system.cpu1.BPredUnit.BTBHits                 1155732                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups              2684041                       # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect               8261                       # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.condIncorrect            171129                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.condPredicted           2476500                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups                 2988933                       # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS                  209112                       # Number of times the RAS was used to get a target.
+system.cpu1.commit.COM:branches               1513156                       # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events           195927                       # number cycles where commit BW limit reached
 system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples     19921603                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean     0.539460                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev     1.350836                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples     17812439                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean     0.593209                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev     1.404519                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0     15476427     77.69%     77.69% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1      2094576     10.51%     88.20% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2       801789      4.02%     92.23% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3       588293      2.95%     95.18% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4       417407      2.10%     97.27% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5       144338      0.72%     98.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6       104661      0.53%     98.52% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7        88312      0.44%     98.97% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8       205800      1.03%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0     13432656     75.41%     75.41% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1      2071277     11.63%     87.04% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2       798332      4.48%     91.52% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3       569921      3.20%     94.72% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4       392752      2.20%     96.93% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5       150104      0.84%     97.77% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6       110432      0.62%     98.39% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7        91038      0.51%     98.90% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8       195927      1.10%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total     19921603                       # Number of insts commited each cycle
-system.cpu1.commit.COM:count                 10746901                       # Number of instructions committed
-system.cpu1.commit.COM:loads                  2021572                       # Number of loads committed
-system.cpu1.commit.COM:membars                  56653                       # Number of memory barriers committed
-system.cpu1.commit.COM:refs                   3430255                       # Number of memory references committed
+system.cpu1.commit.COM:committed_per_cycle::total     17812439                       # Number of insts commited each cycle
+system.cpu1.commit.COM:count                 10566506                       # Number of instructions committed
+system.cpu1.commit.COM:loads                  1991573                       # Number of loads committed
+system.cpu1.commit.COM:membars                  52753                       # Number of memory barriers committed
+system.cpu1.commit.COM:refs                   3374641                       # Number of memory references committed
 system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts           163240                       # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts      10746901                       # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls         172585                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts        1766208                       # The number of squashed insts skipped by commit
-system.cpu1.committedInsts                   10192138                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total             10192138                       # Number of Instructions Simulated
-system.cpu1.cpi                              2.158157                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.158157                       # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses::0        48648                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        48648                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10962.569444                       # average LoadLockedReq miss latency
+system.cpu1.commit.branchMispredicts           163273                       # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts      10566506                       # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls         163051                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts        1705232                       # The number of squashed insts skipped by commit
+system.cpu1.committedInsts                   10039690                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total             10039690                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.952682                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.952682                       # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses::0        46395                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        46395                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11084.323923                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7807.164404                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0        41448                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        41448                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     78930500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.148002                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0         7200                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         7200                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits          570                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     51761500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.136285                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8010.474275                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0        39665                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        39665                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     74597500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145059                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0         6730                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         6730                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits          763                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47798500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128613                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         6630                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0        2081061                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2081061                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 16526.110109                       # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses         5967                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0        2059923                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2059923                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15005.371131                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11960.136769                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11669.279162                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0            1891958                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1891958                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency    3125137000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0      0.090869                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0           189103                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       189103                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits            93175                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1147312000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046096                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0            1864992                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1864992                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency    2925012000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0      0.094630                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0           194931                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       194931                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits            99875                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency   1109235000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046145                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses          95928                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     16183000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0        45890                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        45890                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35468.138068                       # average StoreCondReq miss latency
+system.cpu1.dcache.ReadReq_mshr_misses          95056                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     17677500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses::0        43203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        43203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13176.417292                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32471.951759                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0         36851                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        36851                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency    320596500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.196971                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0         9039                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         9039                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency    293481500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.196949                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10174.605229                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0         39340                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        39340                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency     50900500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089415                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0         3863                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3863                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39304500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089415                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses         9038                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0       1356401                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1356401                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 48468.442060                       # average WriteReq miss latency
+system.cpu1.dcache.StoreCondReq_mshr_misses         3863                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses::0       1333474                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1333474                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 21222.665351                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 50000.550136                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18784.142303                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0           1038709                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1038709                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency  15398036295                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0     0.234217                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0          317692                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       317692                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits          255162                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency   3126534400                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.046100                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0           1083830                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1083830                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency   5298111069                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0     0.187213                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0          249644                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       249644                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits          201142                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency    911068470                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036373                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         62530                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    383884000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11747.407108                       # average number of cycles each access was blocked
+system.cpu1.dcache.WriteReq_mshr_misses         48502                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377673500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9931.219300                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 23.303685                       # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs            12380                       # number of cycles access was blocked
+system.cpu1.dcache.avg_refs                 22.846422                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs             5285                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs    145432900                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs     52486494                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         3437462                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0         3393397                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3437462                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 36549.637023                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::total      3393397                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 18496.593531                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 26971.477616                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             2930667                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14073.081751                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0             2948822                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2930667                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency    18523173295                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.147433                       # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total         2948822                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     8223123069                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0       0.131012                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0            506795                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0            444575                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        506795                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits            348337                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   4273846400                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.046097                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_misses::total        444575                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits            301017                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency   2020303470                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.042305                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses          158458                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses          143558                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.929332                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0           475.817757                       # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0        3437462                       # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0                  0.932894                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0           477.641661                       # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0        3393397                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3437462                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 36549.637023                       # average overall miss latency
+system.cpu1.dcache.overall_accesses::total      3393397                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 18496.593531                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 26971.477616                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14073.081751                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            2930667                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            2948822                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2930667                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency   18523173295                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.147433                       # miss rate for overall accesses
+system.cpu1.dcache.overall_hits::total        2948822                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    8223123069                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate::0      0.131012                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0           506795                       # number of overall misses
+system.cpu1.dcache.overall_misses::0           444575                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       506795                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits           348337                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   4273846400                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.046097                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_misses::total       444575                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits           301017                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency   2020303470                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.042305                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses         158458                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    400067000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses         143558                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    395351000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                131481                       # number of replacements
-system.cpu1.dcache.sampled_refs                131801                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                132490                       # number of replacements
+system.cpu1.dcache.sampled_refs                132884                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               475.817757                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3071449                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1882597271000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   66520                       # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles       8690485                       # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred          7262                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved       129460                       # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts       14175016                       # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles          8601755                       # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles           2517670                       # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles         311026                       # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts         21330                       # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles        111692                       # Number of cycles decode is unblocking
-system.cpu1.dtb.data_accesses                  379731                       # DTB accesses
-system.cpu1.dtb.data_acv                           79                       # DTB access violations
-system.cpu1.dtb.data_hits                     3682802                       # DTB hits
-system.cpu1.dtb.data_misses                     10764                       # DTB misses
+system.cpu1.dcache.tagsinuse               477.641661                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 3035924                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1877659074000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                   88699                       # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles       6971990                       # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred          7938                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved       127719                       # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts       13891801                       # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles          8246933                       # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles           2493797                       # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles         302659                       # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts         23688                       # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles         99718                       # Number of cycles decode is unblocking
+system.cpu1.dtb.data_accesses                  452227                       # DTB accesses
+system.cpu1.dtb.data_acv                          183                       # DTB access violations
+system.cpu1.dtb.data_hits                     3607185                       # DTB hits
+system.cpu1.dtb.data_misses                     12842                       # DTB misses
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  273464                       # DTB read accesses
-system.cpu1.dtb.read_acv                           11                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2232523                       # DTB read hits
-system.cpu1.dtb.read_misses                      8601                       # DTB read misses
-system.cpu1.dtb.write_accesses                 106267                       # DTB write accesses
-system.cpu1.dtb.write_acv                          68                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1450279                       # DTB write hits
-system.cpu1.dtb.write_misses                     2163                       # DTB write misses
-system.cpu1.fetch.Branches                    3058879                       # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines                  1688815                       # Number of cache lines fetched
-system.cpu1.fetch.Cycles                      4357354                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes               105751                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts                      14416907                       # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles                 179                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles                 193553                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate                 0.139064                       # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles           1688815                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches           1382928                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate                       0.655426                       # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples          20232629                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.712557                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.050166                       # Number of instructions fetched each cycle (Total)
+system.cpu1.dtb.read_accesses                  320739                       # DTB read accesses
+system.cpu1.dtb.read_acv                           82                       # DTB read access violations
+system.cpu1.dtb.read_hits                     2181924                       # DTB read hits
+system.cpu1.dtb.read_misses                     10502                       # DTB read misses
+system.cpu1.dtb.write_accesses                 131488                       # DTB write accesses
+system.cpu1.dtb.write_acv                         101                       # DTB write access violations
+system.cpu1.dtb.write_hits                    1425261                       # DTB write hits
+system.cpu1.dtb.write_misses                     2340                       # DTB write misses
+system.cpu1.fetch.Branches                    2988933                       # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines                  1669639                       # Number of cache lines fetched
+system.cpu1.fetch.Cycles                      4303594                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes               104390                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts                      14140107                       # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles                 288                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles                 190275                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate                 0.152463                       # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles           1669639                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches           1364844                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate                       0.721275                       # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples          18115098                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.780570                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.128559                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                17569535     86.84%     86.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  215879      1.07%     87.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  322874      1.60%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  192834      0.95%     90.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  374265      1.85%     92.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  129017      0.64%     92.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  159403      0.79%     93.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  272361      1.35%     95.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  996461      4.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                15489559     85.51%     85.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  208264      1.15%     86.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  323571      1.79%     88.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  199234      1.10%     89.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  375752      2.07%     91.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  125718      0.69%     92.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  169462      0.94%     93.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  249675      1.38%     94.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  973863      5.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            20232629                       # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses::0        1688815                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1688815                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14598.075134                       # average ReadReq miss latency
+system.cpu1.fetch.rateDist::total            18115098                       # Number of instructions fetched each cycle (Total)
+system.cpu1.icache.ReadReq_accesses::0        1669639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1669639                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14675.575285                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11541.965319                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0            1410406                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1410406                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    4064235500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0      0.164855                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0           278409                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       278409                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits             7888                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency   3122344000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.160184                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11632.875773                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0            1406074                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1406074                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    3867968000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate::0      0.157857                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0           263565                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       263565                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits             8225                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency   2970338500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152931                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses         270521                       # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs         8125                       # average number of cycles each access was blocked
+system.cpu1.icache.ReadReq_mshr_misses         255340                       # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5055.555556                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                  5.214764                       # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs                8                       # number of cycles access was blocked
+system.cpu1.icache.avg_refs                  5.507925                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs        65000                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs        45500                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0         1688815                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::0         1669639                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1688815                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14598.075134                       # average overall miss latency
+system.cpu1.icache.demand_accesses::total      1669639                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14675.575285                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11541.965319                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0             1410406                       # number of demand (read+write) hits
+system.cpu1.icache.demand_avg_mshr_miss_latency 11632.875773                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits::0             1406074                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1410406                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     4064235500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.164855                       # miss rate for demand accesses
+system.cpu1.icache.demand_hits::total         1406074                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     3867968000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate::0       0.157857                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0            278409                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::0            263565                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        278409                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits              7888                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   3122344000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0     0.160184                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_misses::total        263565                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits              8225                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency   2970338500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate::0     0.152931                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses          270521                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses          255340                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.900098                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0           460.849961                       # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0        1688815                       # number of overall (read+write) accesses
+system.cpu1.icache.occ_%::0                  0.900435                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0           461.022508                       # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0        1669639                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1688815                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14598.075134                       # average overall miss latency
+system.cpu1.icache.overall_accesses::total      1669639                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14675.575285                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11541.965319                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11632.875773                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0            1410406                       # number of overall hits
+system.cpu1.icache.overall_hits::0            1406074                       # number of overall hits
 system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1410406                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    4064235500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.164855                       # miss rate for overall accesses
+system.cpu1.icache.overall_hits::total        1406074                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    3867968000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate::0      0.157857                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0           278409                       # number of overall misses
+system.cpu1.icache.overall_misses::0           263565                       # number of overall misses
 system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       278409                       # number of overall misses
-system.cpu1.icache.overall_mshr_hits             7888                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   3122344000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0     0.160184                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_misses::total       263565                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits             8225                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency   2970338500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate::0     0.152931                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses         270521                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses         255340                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                269955                       # number of replacements
-system.cpu1.icache.sampled_refs                270464                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                254770                       # number of replacements
+system.cpu1.icache.sampled_refs                255282                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               460.849961                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1410406                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1902950008000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.idleCycles                        1763601                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches                 1647161                       # Number of branches executed
-system.cpu1.iew.EXEC:nop                       633873                       # number of nop insts executed
-system.cpu1.iew.EXEC:rate                    0.498846                       # Inst execution rate
-system.cpu1.iew.EXEC:refs                     3712298                       # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores                   1459673                       # Number of stores executed
+system.cpu1.icache.tagsinuse               461.022508                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1406074                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1897916485000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                      12                       # number of writebacks
+system.cpu1.idleCycles                        1489226                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches                 1621685                       # Number of branches executed
+system.cpu1.iew.EXEC:nop                       600518                       # number of nop insts executed
+system.cpu1.iew.EXEC:rate                    0.550648                       # Inst execution rate
+system.cpu1.iew.EXEC:refs                     3638770                       # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores                   1434645                       # Number of stores executed
 system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu1.iew.WB:consumers                  6255206                       # num instructions consuming a value
-system.cpu1.iew.WB:count                     10847139                       # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout                    0.739229                       # average fanout of values written-back
+system.cpu1.iew.WB:consumers                  6221893                       # num instructions consuming a value
+system.cpu1.iew.WB:count                     10690151                       # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout                    0.737580                       # average fanout of values written-back
 system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers                  4624029                       # num instructions producing a value
-system.cpu1.iew.WB:rate                      0.493136                       # insts written-back per cycle
-system.cpu1.iew.WB:sent                      10867556                       # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts              177268                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles                 332920                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts              2358529                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts            525453                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts           201798                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts             1538474                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts           12592629                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts              2252625                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           104488                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts             10972727                       # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents                  3148                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.WB:producers                  4589145                       # num instructions producing a value
+system.cpu1.iew.WB:rate                      0.545296                       # insts written-back per cycle
+system.cpu1.iew.WB:sent                      10713297                       # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts              177050                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles                 257506                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts              2306314                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts            500674                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts           208241                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts             1509678                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts           12354884                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts              2204125                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           106415                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts             10795075                       # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents                  2676                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents                 1572                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles                311026                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles                 9766                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewLSQFullEvents                 4880                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                302659                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles                10387                       # Number of cycles IEW is unblocking
 system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked        50281                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads          68629                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses         4124                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.cacheBlocked        20658                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads          67397                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses         2150                       # Number of memory responses ignored because the instruction is squashed
 system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation         9401                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread.0.rescheduledLoads          371                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads       336957                       # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores       129791                       # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents          9401                       # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect       104860                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect         72408                       # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc                              0.463358                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.463358                       # IPC: Total IPC of All Threads
-system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3519      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6926354     62.53%     62.56% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult         18692      0.17%     62.73% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.73% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11838      0.11%     62.84% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     62.84% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     62.84% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.84% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1759      0.02%     62.85% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.85% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead       2331483     21.05%     83.90% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1476157     13.33%     97.22% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307413      2.78%    100.00% # Type of FU issued
+system.cpu1.iew.lsq.thread.0.memOrderViolation        10614                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads          379                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads       314741                       # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores       126610                       # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents         10614                       # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect       104614                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect         72436                       # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc                              0.512116                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.512116                       # IPC: Total IPC of All Threads
+system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3525      0.03%      0.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6828006     62.63%     62.67% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult         17554      0.16%     62.83% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.83% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     62.93% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     62.93% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     62.93% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     62.93% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     62.95% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     62.95% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead       2279720     20.91%     83.86% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1451557     13.32%     97.18% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307934      2.82%    100.00% # Type of FU issued
 system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total        11077215                       # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt               158215                       # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate            0.014283                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total        10901490                       # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt               154119                       # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate            0.014137                       # FU busy rate (busy events/executed inst)
 system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu             4066      2.57%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.57% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead           92866     58.70%     61.27% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite          61283     38.73%    100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu             3997      2.59%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.59% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead           90686     58.84%     61.43% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite          59436     38.57%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples     20232629                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.547493                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.152304                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples     18115098                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.601790                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.204979                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0     14868449     73.49%     73.49% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1      2672522     13.21%     86.70% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2      1102181      5.45%     92.14% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3       699877      3.46%     95.60% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4       518299      2.56%     98.16% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5       241576      1.19%     99.36% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6        93786      0.46%     99.82% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7        30604      0.15%     99.97% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8         5335      0.03%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0     12897978     71.20%     71.20% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1      2566961     14.17%     85.37% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2      1067808      5.89%     91.27% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3       689821      3.81%     95.07% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4       522358      2.88%     97.96% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5       233805      1.29%     99.25% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6        92642      0.51%     99.76% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7        34659      0.19%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8         9066      0.05%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total     20232629                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate                    0.503596                       # Inst issue rate
-system.cpu1.iq.iqInstsAdded                  11373839                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued                 11077215                       # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded             584917                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined        1698901                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued            10384                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved        412332                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined       877867                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.ISSUE:issued_per_cycle::total     18115098                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate                    0.556076                       # Inst issue rate
+system.cpu1.iq.iqInstsAdded                  11198244                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued                 10901490                       # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded             556122                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined        1641267                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued            10273                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved        393071                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined       839516                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_hits                           0                       # DTB hits
 system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                 413824                       # ITB accesses
-system.cpu1.itb.fetch_acv                         100                       # ITB acv
-system.cpu1.itb.fetch_hits                     408478                       # ITB hits
-system.cpu1.itb.fetch_misses                     5346                       # ITB misses
+system.cpu1.itb.fetch_accesses                 447863                       # ITB accesses
+system.cpu1.itb.fetch_acv                         278                       # ITB acv
+system.cpu1.itb.fetch_hits                     439724                       # ITB hits
+system.cpu1.itb.fetch_misses                     8139                       # ITB misses
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -1006,95 +1006,105 @@ system.cpu1.itb.write_acv                           0                       # DT
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  300      0.50%      0.50% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.50% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.50% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1497      2.49%      3.00% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  254      0.44%      0.45% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.45% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1450      2.54%      2.99% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      12      0.02%      3.01% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      3.02% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                52375     87.24%     90.26% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2373      3.95%     94.21% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.21% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.22% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.22% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3300      5.50%     99.72% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 124      0.21%     99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.07%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                49382     86.51%     89.53% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2383      4.17%     93.71% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.71% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     93.71% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     2      0.00%     93.72% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.72% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3352      5.87%     99.60% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 187      0.33%     99.92% # number of callpals executed
+system.cpu1.kern.callpal::imb                      43      0.08%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 60033                       # number of callpals executed
+system.cpu1.kern.callpal::total                 57084                       # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     66427                       # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce                    2553                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count::0                   21855     37.68%     37.68% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1927      3.32%     41.01% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    393      0.68%     41.68% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  33821     58.32%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               57996                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    21257     47.83%     47.83% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1927      4.34%     52.17% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     393      0.88%     53.05% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   20864     46.95%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                44441                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1874788065000     98.35%     98.35% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              349524500      0.02%     98.37% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              166729500      0.01%     98.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            30954744500      1.62%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1906259063500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.972638                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei                     64923                       # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce                    2510                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count::0                   20673     37.58%     37.58% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1922      3.49%     41.08% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    351      0.64%     41.71% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  32062     58.29%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               55008                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    20166     47.73%     47.73% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1922      4.55%     52.27% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     351      0.83%     53.11% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   19815     46.89%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                42254                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1870782192000     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              347977500      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              137627500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29209741000      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900477538000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.975475                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.616895                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel                700                      
-system.cpu1.kern.mode_good::user                  383                      
-system.cpu1.kern.mode_good::idle                  317                      
-system.cpu1.kern.mode_switch::kernel             1588                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                383                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2627                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel     0.440806                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used::31                0.618021                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good::kernel                849                      
+system.cpu1.kern.mode_good::user                  573                      
+system.cpu1.kern.mode_good::idle                  276                      
+system.cpu1.kern.mode_switch::kernel             1769                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                573                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2540                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good::kernel     0.479932                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.120670                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.561476                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        7544739000      0.40%      0.40% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           853569500      0.04%      0.44% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1897425262500     99.56%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1498                       # number of times the context was actually changed
-system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
-system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
-system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
-system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
-system.cpu1.memDep0.conflictingLoads           510972                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          447437                       # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads             2358529                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1538474                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles                        21996230                       # number of cpu cycles simulated
-system.cpu1.rename.RENAME:BlockCycles          659886                       # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps       7238905                       # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents          29431                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles          8848928                       # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents        376341                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents          2702                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups      15628999                       # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts       13115251                       # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands      8582665                       # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles           2365502                       # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles         311026                       # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles        913464                       # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps          1343760                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles      7133821                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts       521569                       # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts           2485864                       # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts        55479                       # count of temporary serializing insts renamed
-system.cpu1.timesIdled                         207727                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.kern.mode_switch_good::idle      0.108661                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.588594                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        6304093000      0.33%      0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1020319500      0.05%      0.39% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893140641500     99.61%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1451                       # number of times the context was actually changed
+system.cpu1.kern.syscall::2                         2      1.60%      1.60% # number of syscalls executed
+system.cpu1.kern.syscall::3                        13     10.40%     12.00% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.80%     12.80% # number of syscalls executed
+system.cpu1.kern.syscall::6                        15     12.00%     24.80% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.80%     25.60% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      4.80%     30.40% # number of syscalls executed
+system.cpu1.kern.syscall::19                        4      3.20%     33.60% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.60%     35.20% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.40%     37.60% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.40%     40.00% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.20%     43.20% # number of syscalls executed
+system.cpu1.kern.syscall::45                       18     14.40%     57.60% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.40%     60.00% # number of syscalls executed
+system.cpu1.kern.syscall::48                        3      2.40%     62.40% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.80%     63.20% # number of syscalls executed
+system.cpu1.kern.syscall::59                        2      1.60%     64.80% # number of syscalls executed
+system.cpu1.kern.syscall::71                       27     21.60%     86.40% # number of syscalls executed
+system.cpu1.kern.syscall::74                        9      7.20%     93.60% # number of syscalls executed
+system.cpu1.kern.syscall::90                        2      1.60%     95.20% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.60%     96.80% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.40%     99.20% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.80%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   125                       # number of syscalls executed
+system.cpu1.memDep0.conflictingLoads           493721                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          420829                       # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads             2306314                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1509678                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.numCycles                        19604324                       # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles          523322                       # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps       7130376                       # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents          34965                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles          8479727                       # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents        256792                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents         15396                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups      15372563                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts       12869198                       # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands      8442140                       # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles           2348315                       # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles         302659                       # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles        803488                       # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps          1311764                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles      5657585                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts       515686                       # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts           2307049                       # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts        52733                       # count of temporary serializing insts renamed
+system.cpu1.timesIdled                         194546                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1110,14 +1120,14 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iocache.ReadReq_accesses::1                172                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            172                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115273.244186                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115267.430233                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency          19826998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          19825998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_misses::1                  172                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              172                       # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency     10882998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     10881998                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
@@ -1125,37 +1135,37 @@ system.iocache.ReadReq_mshr_misses                172                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137834.973190                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137710.430449                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85831.529120                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5727318806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85706.873219                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5722143806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3566471698                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561291996                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6167.680658                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6177.017118                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64507772                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64593068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41724                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137741.966350                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137617.913048                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85738.536478                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85614.370482                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5747145804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741969804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -1163,7 +1173,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41724                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3577354696                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572173994                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -1171,20 +1181,20 @@ system.iocache.demand_mshr_misses               41724                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.029720                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 0.475524                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.029205                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 0.467285                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41724                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137741.966350                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137617.913048                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85738.536478                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85614.370482                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5747145804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741969804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -1192,7 +1202,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41724                       # number of overall misses
 system.iocache.overall_misses::total            41724                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3577354696                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572173994                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -1202,196 +1212,196 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41692                       # number of replacements
 system.iocache.sampled_refs                     41708                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     0.475524                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.467285                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1715203940000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1711286407000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               257631                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                41153                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           298784                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 60735.824013                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 380275.607871                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               257280                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                42301                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           299581                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 55984.106319                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 837903.858521                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40207.175331                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                     1663                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                      271                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 1934                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency         15546427401                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.993545                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.993415                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 255968                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  40882                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             296850                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    11935499997                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       1.152229                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       7.213326                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40324.237567                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   140913                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    34526                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               175439                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6514702500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.452297                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.183802                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 116367                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   7775                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124142                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     5005931500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.482517                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       2.934730                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               296850                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                1795093                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 360112                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2155205                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52872.781104                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   3365794.496366                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               124142                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                1807521                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 343124                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2150645                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52801.759863                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   3686733.249197                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40019.494912                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40018.781571                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1488578                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     355297                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1843875                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16206300500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.170752                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.013371                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   306515                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4815                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               311330                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                       18                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12458549000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.173424                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.864487                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0                    1503236                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     338766                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1842002                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16066783500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.168344                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.012701                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   304285                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4358                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               308643                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                       16                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency      12350876500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.170746                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.899462                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 311312                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    840831000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0             14188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1              5331                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         19519                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 67372.602257                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 179272.565209                       # average SCUpgradeReq miss latency
+system.l2c.ReadReq_mshr_misses                 308627                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    840467500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_accesses::0               597                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1               609                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1206                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_avg_miss_latency::0  4976.234004                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1  4685.025818                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.251217                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_hits::0                     8                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                     2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency        955343500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0         0.999436                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.999625                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               14180                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                5329                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           19509                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency    780579500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.375035                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     3.659539                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40010.195035                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_hits::0                    50                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                    28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                78                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_miss_latency          2722000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_rate::0         0.916248                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.954023                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0                 547                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                 581                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1128                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_mshr_miss_latency     45131500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.889447                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.852217                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses             19509                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0               55251                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1               16863                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           72114                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 64253.326605                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 210525.121307                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_mshr_misses              1128                       # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0                2889                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                1652                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4541                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0  5869.326501                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 12325.134512                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.687237                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                      16                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                       5                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  21                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency         3549032495                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.999710                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.999703                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 55235                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                 16858                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             72093                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    2885283498                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.304827                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      4.275218                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.488966                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                     157                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     351                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 508                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency           16035000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.945656                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.787530                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  2732                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                  1301                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4033                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency     161386500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.395985                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      2.441283                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               72093                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                4033                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1554057498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               446200                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           446200                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   446200                       # number of Writeback hits
-system.l2c.Writeback_hits::total               446200                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1532909498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               810428                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           810428                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   810428                       # number of Writeback hits
+system.l2c.Writeback_hits::total               810428                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.752489                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.655479                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2052724                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  401265                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2064801                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  385425                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2453989                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    56451.000121                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    694853.664376                       # average overall miss latency
+system.l2c.demand_accesses::total             2450226                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    53682.107776                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1861162.614358                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40111.103615                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1490241                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      355568                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40106.403185                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1644149                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      373292                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1845809                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31752727901                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.274018                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.113882                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 2017441                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22581486000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.203725                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.031480                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    562483                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     45697                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    420652                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     12133                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                608180                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                        18                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24394048997                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.296271                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.515612                       # mshr miss rate for demand accesses
+system.l2c.demand_misses::total                432785                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                        16                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency       17356808000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.209594                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.122836                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  608162                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  432769                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.174396                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.005052                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.332288                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 11429.229058                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   331.081192                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 21776.825321                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2052724                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 401265                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.187903                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.005747                       # Average percentage of cache occupancy
+system.l2c.occ_%::2                          0.351863                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 12314.431078                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   376.630124                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23059.694781                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2064801                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 385425                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2453989                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   56451.000121                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   694853.664376                       # average overall miss latency
+system.l2c.overall_accesses::total            2450226                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   53682.107776                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1861162.614358                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40111.103615                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40106.403185                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1490241                       # number of overall hits
-system.l2c.overall_hits::1                     355568                       # number of overall hits
+system.l2c.overall_hits::0                    1644149                       # number of overall hits
+system.l2c.overall_hits::1                     373292                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                1845809                       # number of overall hits
-system.l2c.overall_miss_latency           31752727901                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.274018                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.113882                       # miss rate for overall accesses
+system.l2c.overall_hits::total                2017441                       # number of overall hits
+system.l2c.overall_miss_latency           22581486000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.203725                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.031480                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   562483                       # number of overall misses
-system.l2c.overall_misses::1                    45697                       # number of overall misses
+system.l2c.overall_misses::0                   420652                       # number of overall misses
+system.l2c.overall_misses::1                    12133                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               608180                       # number of overall misses
-system.l2c.overall_mshr_hits                       18                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24394048997                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.296271                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.515612                       # mshr miss rate for overall accesses
+system.l2c.overall_misses::total               432785                       # number of overall misses
+system.l2c.overall_mshr_hits                       16                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency      17356808000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.209594                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.122836                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 608162                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2394888498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 432769                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2373376998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        399060                       # number of replacements
-system.l2c.sampled_refs                        435274                       # Sample count of references to valid blocks.
+system.l2c.replacements                        395546                       # number of replacements
+system.l2c.sampled_refs                        431605                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     33537.135570                       # Cycle average of tags in use
-system.l2c.total_refs                         2068635                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                    9277782000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          122307                       # number of writebacks
+system.l2c.tagsinuse                     35750.755983                       # Cycle average of tags in use
+system.l2c.total_refs                         2440933                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                    9270445000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          121345                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 208609d63..422a343b6 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -356,7 +356,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -376,7 +376,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -502,7 +502,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index f8d53b80a..bdccd9639 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:33
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:17:56
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1865288389500 because m5_exit instruction encountered
+Exiting @ tick 1865720303500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index df900ba3a..eeeafc5e0 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,449 +1,447 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  83534                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 292436                       # Number of bytes of host memory used
-host_seconds                                   635.06                       # Real time elapsed on the host
-host_tick_rate                             2937207030                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 159619                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 280620                       # Number of bytes of host memory used
+host_seconds                                   332.38                       # Real time elapsed on the host
+host_tick_rate                             5613142222                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    53048754                       # Number of instructions simulated
-sim_seconds                                  1.865288                       # Number of seconds simulated
-sim_ticks                                1865288389500                       # Number of ticks simulated
+sim_insts                                    53054978                       # Number of instructions simulated
+sim_seconds                                  1.865720                       # Number of seconds simulated
+sim_ticks                                1865720303500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  6766434                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              12986969                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               41472                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             813466                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           12097848                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 14524578                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1028567                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                8457223                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1009026                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                  6622960                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              12821186                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               40564                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             813627                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           11934155                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 14336611                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1015763                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                8457975                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           1007897                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     98617953                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.570296                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.335991                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     89507255                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.628419                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.391887                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     74454640     75.50%     75.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     10711227     10.86%     86.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      5970777      6.05%     92.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      2911969      2.95%     95.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2119464      2.15%     97.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       692478      0.70%     98.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       398357      0.40%     98.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       350015      0.35%     98.98% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1009026      1.02%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     65378590     73.04%     73.04% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     10678414     11.93%     84.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      6017811      6.72%     91.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      2845727      3.18%     94.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2113660      2.36%     97.24% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5       688870      0.77%     98.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       399291      0.45%     98.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       376995      0.42%     98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      1007897      1.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     98617953                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  56241389                       # Number of instructions committed
-system.cpu.commit.COM:loads                   9301917                       # Number of loads committed
-system.cpu.commit.COM:membars                  227986                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   15690474                       # Number of memory references committed
+system.cpu.commit.COM:committed_per_cycle::total     89507255                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                  56248094                       # Number of instructions committed
+system.cpu.commit.COM:loads                   9303211                       # Number of loads committed
+system.cpu.commit.COM:membars                  227966                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   15692722                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts            771977                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       56241389                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          667741                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts         9346936                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    53048754                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              53048754                       # Number of Instructions Simulated
-system.cpu.cpi                               2.541919                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.541919                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0       214829                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       214829                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15450.383219                       # average LoadLockedReq miss latency
+system.cpu.commit.branchMispredicts            772391                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       56248094                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          667633                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts         8673540                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    53054978                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53054978                       # Number of Instructions Simulated
+system.cpu.cpi                               2.357684                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.357684                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0       215825                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       215825                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14729.331951                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11789.484229                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        192518                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       192518                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    344713500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.103855                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        22311                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22311                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits         4842                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    205950500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081316                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11874.503483                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0        193641                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       193641                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    326755500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.102787                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0        22184                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22184                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits         4813                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    206272000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.080487                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17469                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         9301988                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9301988                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 23801.813261                       # average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses        17371                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses::0         9299177                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9299177                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 22716.761778                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22758.438856                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22778.216619                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             7781909                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7781909                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    36180636500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.163414                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1520079                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1520079                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            436579                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  24658768500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116480                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0             7724529                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7724529                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    35770903500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.169332                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0           1574648                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1574648                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            490606                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  24692543500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116574                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1083500                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    904975000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       219792                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       219792                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56335.990566                       # average StoreCondReq miss latency
+system.cpu.dcache.ReadReq_mshr_misses         1084042                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    906118000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0       219742                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       219742                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53335.990566                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0         198592                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       198592                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency   1194323000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate::0     0.096455                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0        21200                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total        21200                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency   1130723000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.096455                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits::0         219738                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       219738                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency        56000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate::0     0.000018                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency        44000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000018                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses        21200                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0        6153614                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6153614                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 48733.687858                       # average WriteReq miss latency
+system.cpu.dcache.StoreCondReq_mshr_misses            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses::0        6154612                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6154612                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29779.159103                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53794.875061                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.813701                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            3986142                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        3986142                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  105628903889                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.352227                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0          2167472                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2167472                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1799517                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  19794093253                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.059795                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0            4298505                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4298505                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   55273305665                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.301580                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0          1856107                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1856107                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1556374                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   8419743863                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048701                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         367955                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235122997                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  9816.976394                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        17750                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   8.810921                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs            136746                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses         299733                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235249998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  8585.120096                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        14500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                   8.876782                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs             86206                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs   1342432254                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        35500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs    740088863                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15455602                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0         15453789                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15455602                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 38456.292642                       # average overall miss latency
+system.cpu.dcache.demand_accesses::total     15453789                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26537.659834                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30626.414014                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             11768051                       # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23928.953307                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             12023034                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11768051                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    141809540389                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.238590                       # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total         12023034                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     91044209165                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.222001                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            3687551                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            3430755                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3687551                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2236096                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  44452861753                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.093911                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total        3430755                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2046980                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  33112287363                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.089543                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1451455                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1383775                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999991                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_%::1                  -0.007635                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            511.995459                       # Average occupied blocks per context
-system.cpu.dcache.occ_blocks::1             -3.909039                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0        15455602                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0            511.995487                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        15453789                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15455602                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 38456.292642                       # average overall miss latency
+system.cpu.dcache.overall_accesses::total     15453789                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26537.659834                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30626.414014                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23928.953307                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            11768051                       # number of overall hits
+system.cpu.dcache.overall_hits::0            12023034                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11768051                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   141809540389                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.238590                       # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total        12023034                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    91044209165                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.222001                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           3687551                       # number of overall misses
+system.cpu.dcache.overall_misses::0           3430755                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3687551                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2236096                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  44452861753                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.093911                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total       3430755                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2046980                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  33112287363                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.089543                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1451455                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2140097997                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses         1383775                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2141367998                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1400442                       # number of replacements
-system.cpu.dcache.sampled_refs                1400954                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1400502                       # number of replacements
+system.cpu.dcache.sampled_refs                1401014                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                510.040943                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 12343695                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.995487                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12436496                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               21271000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   455265                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       46660710                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          42482                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved        616847                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts        72473028                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          37849528                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           12958836                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1616629                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         135444                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1148878                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                  1239402                       # DTB accesses
-system.cpu.dtb.data_acv                           830                       # DTB access violations
-system.cpu.dtb.data_hits                     16737953                       # DTB hits
-system.cpu.dtb.data_misses                      44771                       # DTB misses
+system.cpu.dcache.writebacks                   832844                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       38077949                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          42141                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved        613000                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts        71339111                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          37499395                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           12847543                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         1512175                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         134289                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1082367                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                  1229801                       # DTB accesses
+system.cpu.dtb.data_acv                           813                       # DTB access violations
+system.cpu.dtb.data_hits                     16587007                       # DTB hits
+system.cpu.dtb.data_misses                      46930                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   913549                       # DTB read accesses
-system.cpu.dtb.read_acv                           594                       # DTB read access violations
-system.cpu.dtb.read_hits                     10142643                       # DTB read hits
-system.cpu.dtb.read_misses                      36670                       # DTB read misses
-system.cpu.dtb.write_accesses                  325853                       # DTB write accesses
-system.cpu.dtb.write_acv                          236                       # DTB write access violations
-system.cpu.dtb.write_hits                     6595310                       # DTB write hits
-system.cpu.dtb.write_misses                      8101                       # DTB write misses
-system.cpu.fetch.Branches                    14524578                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                   8948260                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      23311047                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                456775                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       73989590                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                 2537                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                  952530                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.107713                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles            8948260                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches            7795001                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.548698                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          100234582                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.738164                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.038365                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_accesses                   909497                       # DTB read accesses
+system.cpu.dtb.read_acv                           578                       # DTB read access violations
+system.cpu.dtb.read_hits                     10001234                       # DTB read hits
+system.cpu.dtb.read_misses                      38618                       # DTB read misses
+system.cpu.dtb.write_accesses                  320304                       # DTB write accesses
+system.cpu.dtb.write_acv                          235                       # DTB write access violations
+system.cpu.dtb.write_hits                     6585773                       # DTB write hits
+system.cpu.dtb.write_misses                      8312                       # DTB write misses
+system.cpu.fetch.Branches                    14336611                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                   8856375                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      23007170                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                453326                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       72609191                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                 3119                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                  881894                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.114613                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles            8856375                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches            7638723                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.580470                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           91019430                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.797733                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.106251                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 85912196     85.71%     85.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1042441      1.04%     86.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1978378      1.97%     88.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   936363      0.93%     89.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2989129      2.98%     92.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   664727      0.66%     93.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   787515      0.79%     94.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1214601      1.21%     95.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4709232      4.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 76908614     84.50%     84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1045900      1.15%     85.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1970690      2.17%     87.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   922798      1.01%     88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2985749      3.28%     92.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   648659      0.71%     92.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   777022      0.85%     93.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1074890      1.18%     94.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4685108      5.15%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            100234582                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses::0         8948260                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8948260                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14907.888251                       # average ReadReq miss latency
+system.cpu.fetch.rateDist::total             91019430                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses::0         8856375                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8856375                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14955.618992                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11902.318660                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0             7903415                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7903415                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    15576432500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.116765                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0           1044845                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1044845                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits             50305                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency  11837332000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.111143                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.509769                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0             7815975                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7815975                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    15559825999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.117475                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0           1040400                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1040400                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits             47600                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency  11852552499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.112100                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          994540                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs 12104.838710                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_mshr_misses          992800                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12245.264151                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   7.948315                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                62                       # number of cycles access was blocked
+system.cpu.icache.avg_refs                   7.874156                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                53                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs       750500                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs       648999                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0          8948260                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0          8856375                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8948260                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14907.888251                       # average overall miss latency
+system.cpu.icache.demand_accesses::total      8856375                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14955.618992                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11902.318660                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0              7903415                       # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11938.509769                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0              7815975                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7903415                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     15576432500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.116765                       # miss rate for demand accesses
+system.cpu.icache.demand_hits::total          7815975                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     15559825999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.117475                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0            1044845                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0            1040400                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1044845                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits              50305                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  11837332000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.111143                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total        1040400                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits              47600                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency  11852552499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.112100                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           994540                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses           992800                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.995598                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            509.746088                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0         8948260                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.995724                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            509.810488                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0         8856375                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8948260                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14907.888251                       # average overall miss latency
+system.cpu.icache.overall_accesses::total      8856375                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14955.618992                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11902.318660                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11938.509769                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0             7903415                       # number of overall hits
+system.cpu.icache.overall_hits::0             7815975                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         7903415                       # number of overall hits
-system.cpu.icache.overall_miss_latency    15576432500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.116765                       # miss rate for overall accesses
+system.cpu.icache.overall_hits::total         7815975                       # number of overall hits
+system.cpu.icache.overall_miss_latency    15559825999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.117475                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0           1044845                       # number of overall misses
+system.cpu.icache.overall_misses::0           1040400                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1044845                       # number of overall misses
-system.cpu.icache.overall_mshr_hits             50305                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  11837332000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.111143                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total       1040400                       # number of overall misses
+system.cpu.icache.overall_mshr_hits             47600                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency  11852552499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.112100                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          994540                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses          992800                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 993840                       # number of replacements
-system.cpu.icache.sampled_refs                 994351                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 992100                       # number of replacements
+system.cpu.icache.sampled_refs                 992611                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                509.746088                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7903415                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle            25251004000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        5                       # number of writebacks
-system.cpu.idleCycles                        34611048                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                  9149461                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       3645494                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.426187                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     17021543                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    6618330                       # Number of stores executed
+system.cpu.icache.tagsinuse                509.810488                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7815974                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle            24432976000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                       92                       # number of writebacks
+system.cpu.idleCycles                        34067458                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                  9122615                       # Number of branches executed
+system.cpu.iew.EXEC:nop                       3587548                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.456821                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     16872636                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    6608998                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  34491432                       # num instructions consuming a value
-system.cpu.iew.WB:count                      56873596                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.763558                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  35235161                       # num instructions consuming a value
+system.cpu.iew.WB:count                      56707736                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.757346                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  26336207                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.421768                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       56969504                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts               835772                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 9640204                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              11032857                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            1798988                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           1002562                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              7014115                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts            65718389                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              10403213                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            554442                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              57469408                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  44506                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  26685206                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.453347                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       56809510                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               839127                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 9343071                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              10818405                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            1790311                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            888014                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              6925516                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            65053041                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              10263638                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            522865                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              57142298                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  63050                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  6661                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                1616629                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                544895                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 11753                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                1512175                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                559162                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked       306779                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          434666                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        11993                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked       127334                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          439799                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         8819                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        45591                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        18153                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      1730940                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores       625558                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          45591                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       404736                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         431036                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               0.393404                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.393404                       # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7283      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        39532589     68.13%     68.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          62065      0.11%     68.25% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     68.25% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd         25614      0.04%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv          3637      0.01%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     68.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       10774153     18.57%     86.87% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       6665338     11.49%     98.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess       953173      1.64%    100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation        42451                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        17646                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      1515194                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores       536005                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          42451                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       406021                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         433106                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.424145                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.424145                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7281      0.01%      0.01% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        39339623     68.22%     68.23% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          62341      0.11%     68.34% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd         25607      0.04%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv          3636      0.01%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     68.39% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       10615152     18.41%     86.80% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       6658629     11.55%     98.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess       952896      1.65%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         58023852                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                434401                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.007487                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total         57665165                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                433439                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.007516                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             47887     11.02%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     11.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           281518     64.81%     75.83% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          104996     24.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             48806     11.26%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     11.26% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead           267453     61.70%     72.97% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          117180     27.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    100234582                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.578881                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.146223                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     91019430                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.633548                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.199187                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      71270288     71.10%     71.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      14553068     14.52%     85.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       6335877      6.32%     91.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       3893576      3.88%     95.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2543708      2.54%     98.37% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1056426      1.05%     99.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        441326      0.44%     99.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        109120      0.11%     99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         31193      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      62621832     68.80%     68.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      14091892     15.48%     84.28% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2       6228717      6.84%     91.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       3803889      4.18%     95.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       2535360      2.79%     98.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       1092488      1.20%     99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        467011      0.51%     99.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        127702      0.14%     99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         50539      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    100234582                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.430298                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                   60022452                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  58023852                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             2050443                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined         8631662                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             41705                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved        1382702                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined      4647656                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     91019430                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.461001                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                   59425779                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  57665165                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             2039714                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined         8033204                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             30047                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved        1372081                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined      4119513                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 1304111                       # ITB accesses
-system.cpu.itb.fetch_acv                          934                       # ITB acv
-system.cpu.itb.fetch_hits                     1264639                       # ITB hits
-system.cpu.itb.fetch_misses                     39472                       # ITB misses
+system.cpu.itb.fetch_accesses                 1291442                       # ITB accesses
+system.cpu.itb.fetch_acv                          931                       # ITB acv
+system.cpu.itb.fetch_hits                     1252390                       # ITB hits
+system.cpu.itb.fetch_misses                     39052                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -456,55 +454,55 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4178      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175665     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175588     91.19%     93.39% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6792      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5219      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5222      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192634                       # number of callpals executed
+system.cpu.kern.callpal::total                 192558                       # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211790                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6385                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74955     40.96%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     237      0.13%     41.09% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1888      1.03%     42.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105930     57.88%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183010                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73588     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      237      0.16%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1888      1.26%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73588     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149301                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1823061244500     97.74%     97.74% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                98162000      0.01%     97.74% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               391950000      0.02%     97.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41736158500      2.24%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1865287515000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981762                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei                     211717                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6422                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count::0                    74912     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     242      0.13%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1889      1.03%     42.11% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105896     57.89%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182939                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73545     49.28%     49.28% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      242      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1889      1.27%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73548     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149224                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1826190656000     97.88%     97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                98153500      0.01%     97.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               391767500      0.02%     97.91% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             39038852000      2.09%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1865719429000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694685                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694530                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.mode_good::kernel                1909                      
 system.cpu.kern.mode_good::user                  1739                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch::kernel              5970                       # number of protection mode switches
+system.cpu.kern.mode_switch::kernel              5960                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.319765                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::idle                2106                       # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320302                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.400911                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        31031458000      1.66%      1.66% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           3177312000      0.17%      1.83% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1831078737000     98.17%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4179                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.080722                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.401024                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        30084580500      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           3003065000      0.16%      1.77% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832631775500     98.23%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -536,29 +534,29 @@ system.cpu.kern.syscall::132                        4      1.23%     98.77% # nu
 system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.memDep0.conflictingLoads           3098880                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2694658                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             11032857                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7014115                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                        134845630                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         14093810                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       38225332                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         1080811                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          39441227                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        2214917                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents          14670                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups       83145881                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        68419430                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     45844130                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           12603060                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1616629                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        5180630                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           7618796                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles     27299224                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      1703562                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           12710348                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       255623                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                         1320206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.memDep0.conflictingLoads           2912046                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2554541                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             10818405                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6925516                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                        125086888                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         13518840                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       38230175                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         1063400                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          39070962                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        1708241                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents          58560                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups       82154290                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts        67531938                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     45272379                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           12498732                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         1512175                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        4709748                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps           7042202                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles     19708971                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      1694119                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           11797121                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       247227                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                         1311679                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -589,37 +587,37 @@ system.iocache.ReadReq_mshr_misses                173                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137804.625674                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137713.414661                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85801.092270                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5726057806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85709.809347                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5722267806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3565206986                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561413998                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6169.984712                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6169.345934                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                10466                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64575060                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64630068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137711.103751                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137620.270917                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85707.584997                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85616.680551                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5745995804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5742205804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -627,7 +625,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3576148984                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572355996                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -635,20 +633,20 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.078725                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 1.259600                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.081045                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 1.296712                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137711.103751                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137620.270917                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85707.584997                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85616.680551                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5745995804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5742205804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -656,7 +654,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3576148984                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572355996                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -666,156 +664,144 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.259600                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.296712                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1715198512000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1711281276000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               300711                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300711                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52369.611662                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               300943                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300943                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52461.384650                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40214.373242                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                     2213                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 2213                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency         15632224342                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.992641                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 298498                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             298498                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    12003909984                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.992641                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40312.785193                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   183917                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               183917                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6139346000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.388864                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 117026                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             117026                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4717644000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.388864                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               298498                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                2094821                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2094821                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52048.515602                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               117026                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                2092753                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2092753                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52046.663805                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40015.565251                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40015.758954                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1784931                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1784931                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16129314500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.147931                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   309890                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               309890                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                        1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12400383500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.147931                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0                    1785277                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1785277                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16003100000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.146924                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   307476                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               307476                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency      12303885500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.146924                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 309889                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    810515000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0             21199                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         21199                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 52327.059157                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000.731201                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_hits::0                     1                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency       1109229000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0         0.999953                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               21198                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           21198                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency    847935500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     0.999953                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses             21198                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0               69854                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           69854                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 52150.764423                       # average UpgradeReq miss latency
+system.l2c.ReadReq_mshr_misses                 307476                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    811482500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_accesses::0                 4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_hits::0                     4                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 4                       # number of SCUpgradeReq hits
+system.l2c.UpgradeReq_accesses::0                  27                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              27                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 20722.222222                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40013.263378                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         3642939498                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 69854                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             69854                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    2795086500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0             1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 43333.333333                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                       9                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   9                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency             373000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.666667                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                    18                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                18                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency        780000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.666667                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               69854                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  18                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1115590498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               455270                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           455270                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   455270                       # number of Writeback hits
-system.l2c.Writeback_hits::total               455270                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1115672498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               832936                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           832936                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   832936                       # number of Writeback hits
+system.l2c.Writeback_hits::total               832936                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.693284                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.637084                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2395532                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2393696                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2395532                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52206.057388                       # average overall miss latency
+system.l2c.demand_accesses::total             2393696                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52160.993352                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40113.108078                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1787144                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40097.642650                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1969194                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1787144                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31761538842                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.253968                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 1969194                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22142446000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.177342                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    608388                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    424502                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                608388                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                         1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24404293484                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.253967                       # mshr miss rate for demand accesses
+system.l2c.demand_misses::total                424502                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency       17021529500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.177342                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  608387                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  424502                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.176515                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.325488                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 11568.063937                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 21331.159568                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2395532                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.187192                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.344481                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 12267.817300                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 22575.879516                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2393696                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2395532                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52206.057388                       # average overall miss latency
+system.l2c.overall_accesses::total            2393696                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52160.993352                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40113.108078                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40097.642650                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1787144                       # number of overall hits
+system.l2c.overall_hits::0                    1969194                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1787144                       # number of overall hits
-system.l2c.overall_miss_latency           31761538842                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.253968                       # miss rate for overall accesses
+system.l2c.overall_hits::total                1969194                       # number of overall hits
+system.l2c.overall_miss_latency           22142446000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.177342                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   608388                       # number of overall misses
+system.l2c.overall_misses::0                   424502                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               608388                       # number of overall misses
-system.l2c.overall_mshr_hits                        1                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24404293484                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.253967                       # mshr miss rate for overall accesses
+system.l2c.overall_misses::total               424502                       # number of overall misses
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency      17021529500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.177342                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 608387                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1926105498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 424502                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1927154998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        394069                       # number of replacements
-system.l2c.sampled_refs                        426267                       # Sample count of references to valid blocks.
+system.l2c.replacements                        391012                       # number of replacements
+system.l2c.sampled_refs                        423751                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     32899.223505                       # Cycle average of tags in use
-system.l2c.total_refs                         2000592                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                    5644310000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          118209                       # number of writebacks
+system.l2c.tagsinuse                     34843.696815                       # Cycle average of tags in use
+system.l2c.total_refs                         2388720                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                    5637119000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          117653                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
index 5e9ca96c9..b3a86bf7b 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
index de9fd3dbd..9d6057d13 100755
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 14:11:34
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:14:22
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 152155526000 because target called exit()
+Exiting @ tick 148086219000 because target called exit()
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 82be14609..7d95e3dd8 100644
--- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1008175                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 344580                       # Number of bytes of host memory used
-host_seconds                                    90.44                       # Real time elapsed on the host
-host_tick_rate                             1682447495                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1157512                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 330420                       # Number of bytes of host memory used
+host_seconds                                    78.77                       # Real time elapsed on the host
+host_tick_rate                             1880000368                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91176087                       # Number of instructions simulated
-sim_seconds                                  0.152156                       # Number of seconds simulated
-sim_ticks                                152155526000                       # Number of ticks simulated
+sim_seconds                                  0.148086                       # Number of seconds simulated
+sim_ticks                                148086219000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           22564820                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.157105                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157105                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               21664622                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12615288000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    12614616000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.039894                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               900198                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9914694000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   9914022000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.039894                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          900198                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           4738868                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55998.688893                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.688893                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               4642766                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5381586000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.020280                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               96102                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5093280000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.020280                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          96102                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               4692259                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.009835                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009835                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  27.837649                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            27303688                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18063.709726                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15063.709726                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26307388                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     17996874000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.036490                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                996300                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 14657.853184                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11657.853184                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26356881                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     13878158000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.034677                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                946807                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  15007974000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.036490                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           996300                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  11037737000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.034677                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           946807                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.874745                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3582.956819                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.871309                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3568.882850                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           27303688                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18063.709726                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15063.709726                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 14657.853184                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11657.853184                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26307388                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    17996874000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.036490                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               996300                       # number of overall misses
+system.cpu.dcache.overall_hits               26356881                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    13878158000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.034677                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               946807                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  15007974000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.036490                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          996300                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  11037737000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.034677                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          946807                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 942711                       # number of replacements
 system.cpu.dcache.sampled_refs                 946807                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3582.956819                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3568.882850                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26356881                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            54487870000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    96132                       # number of writebacks
+system.cpu.dcache.warmup_cycle            54482100000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   942313                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses                       0                       # DT
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
 system.cpu.icache.ReadReq_accesses          107819118                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54667.779633                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51667.779633                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              107818519                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32746000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     30949000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           107819118                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54667.779633                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51667.779633                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               107818519                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32746000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     30949000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.249735                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            511.457636                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.249185                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            510.330850                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          107819118                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54667.779633                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              107818519                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32746000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  599                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     30949000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      2                       # number of replacements
 system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                511.457636                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                510.330850                       # Cycle average of tags in use
 system.cpu.icache.total_refs                107818519                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2423512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999936                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             46606                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1864240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999936                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        46606                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            900797                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                899919                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      45656000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.000975                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                 878                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     35120000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000975                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses            878                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          49493                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   2573636000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            49493                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   1979720000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        49493                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           96132                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               96132                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                899937                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          942313                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              942313                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 52.533433                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                103.596349                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             947406                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 899922                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     2469168000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.050120                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                47484                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 931998                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.016263                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   1899360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.050120                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           47484                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.016263                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.009784                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.265384                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           320.609441                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8696.109935                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.009921                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.271910                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           325.103802                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8909.939708                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            947406                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                899922                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    2469168000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.050120                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               47484                       # number of overall misses
+system.cpu.l2cache.overall_hits                931998                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.016263                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               15408                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   1899360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.050120                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          47484                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.016263                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                   678                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15344                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                   634                       # number of replacements
+system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              9016.719375                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  806073                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              9235.043509                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1594555                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                      35                       # number of writebacks
+system.cpu.l2cache.writebacks                      32                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        304311052                       # number of cpu cycles simulated
+system.cpu.numCycles                        296172438                       # number of cpu cycles simulated
 system.cpu.num_insts                         91176087                       # Number of instructions executed
 system.cpu.num_refs                          27330336                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             442                       # Number of system calls
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
index dbbbea9b7..e885b2b99 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
index afcf30904..b2d326b66 100755
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:06:13
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:31:43
+M5 executing on phenom
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 366433850000 because target called exit()
+Exiting @ tick 362430887000 because target called exit()
diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 14b141378..f56720371 100644
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 994564                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 343716                       # Number of bytes of host memory used
-host_seconds                                   245.17                       # Real time elapsed on the host
-host_tick_rate                             1494621764                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1229097                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 329428                       # Number of bytes of host memory used
+host_seconds                                   198.39                       # Real time elapsed on the host
+host_tick_rate                             1826897848                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   243835278                       # Number of instructions simulated
-sim_seconds                                  0.366434                       # Number of seconds simulated
-sim_ticks                                366433850000                       # Number of ticks simulated
+sim_seconds                                  0.362431                       # Number of seconds simulated
+sim_ticks                                362430887000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               81327577                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    12508650000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    12508482000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               892857                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9830079000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   9829911000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          892857                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                   3878                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency         448000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.002059                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                    8                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency       424000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.002059                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses               8                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency        24500                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        21500                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                   3882                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency          98000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.001029                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                    4                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.001029                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses               4                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          22901951                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55998.672804                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.672804                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              22807014                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5316346000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.004145                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               94937                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5031535000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.004145                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          94937                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              22855241                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.002040                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               46710                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.002040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          46710                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
@@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18045.256400                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15045.256400                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               104134591                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     17824996000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.009397                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                987794                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 14660.150899                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               104182818                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.008938                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                939567                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  14861614000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.009397                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           987794                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.008938                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.871491                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3569.628477                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3563.824259                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18045.256400                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15045.256400                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 14660.150899                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              104134591                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    17824996000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.009397                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               987794                       # number of overall misses
+system.cpu.dcache.overall_hits              104182818                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    13774194000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.008938                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               939567                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  14861614000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.009397                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          987794                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.008938                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 935475                       # number of replacements
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3569.628477                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3563.824259                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134378918000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    94947                       # number of writebacks
+system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   935237                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55904.761905                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55857.142857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              244420630                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       49308000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       49266000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  882                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     46662000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     46620000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             882                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           244421512                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55904.761905                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55857.142857                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               244420630                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        49308000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        49266000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   882                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     46662000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     46620000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.354611                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            726.243472                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            725.567632                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55904.761905                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55857.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              244420630                       # number of overall hits
-system.cpu.icache.overall_miss_latency       49308000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       49266000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  882                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     46662000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     46620000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     25                       # number of replacements
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                726.243472                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                725.567632                       # Cycle average of tags in use
 system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -142,37 +142,28 @@ system.cpu.idle_fraction                            0                       # Pe
 system.cpu.l2cache.ReadExReq_accesses           46714                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   2428972000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999936                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             46711                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1868440000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999936                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        46711                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits               32147                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             14567                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        14567                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            893739                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                892653                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency      56472000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.001215                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                1086                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     43440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001215                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           1086                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          48231                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   2508012000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            48231                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   1929240000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        48231                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           94947                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               94947                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                892658                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      56212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.001210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                1081                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     43240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           1081                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              935237                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 51.538160                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                101.457616                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             940453                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 892656                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     2485444000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.050823                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                47797                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 924805                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      813696000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.016639                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                15648                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   1911880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.050823                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses           47797                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    625920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.016639                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           15648                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.011380                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.262199                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0           372.883816                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8591.744977                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.011460                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.270424                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           375.506440                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8861.245791                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                892656                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    2485444000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.050823                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses               47797                       # number of overall misses
+system.cpu.l2cache.overall_hits                924805                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     813696000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.016639                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               15648                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   1911880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.050823                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses          47797                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    625920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.016639                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          15648                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                   891                       # number of replacements
-system.cpu.l2cache.sampled_refs                 15566                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                   865                       # number of replacements
+system.cpu.l2cache.sampled_refs                 15631                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8964.628794                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  802243                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              9236.752232                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1585884                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                      41                       # number of writebacks
+system.cpu.l2cache.writebacks                      40                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        732867700                       # number of cpu cycles simulated
+system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
 system.cpu.num_insts                        243835278                       # Number of instructions executed
 system.cpu.num_refs                         105711442                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             443                       # Number of system calls
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
index a75b06e16..b40b0b08f 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
index 243f7ada9..7070284ed 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:20:12
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:47:25
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:29:54
+M5 executing on phenom
 command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +28,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 378879619000 because target called exit()
+Exiting @ tick 370010840000 because target called exit()
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 951737b71..5a6f923f1 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1022159                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 344728                       # Number of bytes of host memory used
-host_seconds                                   263.85                       # Real time elapsed on the host
-host_tick_rate                             1435967954                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1130440                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 330088                       # Number of bytes of host memory used
+host_seconds                                   238.58                       # Real time elapsed on the host
+host_tick_rate                             1550911771                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   269696010                       # Number of instructions simulated
-sim_seconds                                  0.378880                       # Number of seconds simulated
-sim_ticks                                378879619000                       # Number of ticks simulated
+sim_seconds                                  0.370011                       # Number of seconds simulated
+sim_ticks                                370010840000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           90779450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15327.890775                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12327.890775                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               88818730                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    30053702000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    28849058000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.021599                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1960720                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  24171542000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  22966898000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1960720                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55478.946733                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52478.946733                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              31241017                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   11025553000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.006321                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              198734                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  10429351000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006321                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         198734                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              31333642                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              106109                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         106109                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 19022.982198                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16022.982198                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               120059747                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     41079255000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.017669                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2159454                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               120152372                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.016911                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2066829                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  34600893000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.017669                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2159454                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          2066829                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995362                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4077.003489                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 19022.982198                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16022.982198                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              120059747                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    41079255000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.017669                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2159454                       # number of overall misses
+system.cpu.dcache.overall_hits              120152372                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    32117851000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.016911                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2066829                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  34600893000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.017669                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2159454                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         2066829                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                2062733                       # number of replacements
 system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4077.003489                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           127444032000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   283281                       # number of writebacks
+system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  1437080                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          217696209                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              808                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.325684                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            667.001102                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -124,91 +124,82 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     24                       # number of replacements
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                667.001102                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                666.191948                       # Cycle average of tags in use
 system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses          106109                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.299104                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                2466                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   5389467000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.976760                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            103643                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4145720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.976760                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       103643                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits               63651                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             42458                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        42458                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           1961528                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1898729                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    3265548000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.032015                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               62799                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   2511960000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.032015                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          62799                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses          92625                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.385965                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   4815980000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses            92625                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   3705000000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses        92625                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          283281                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              283281                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               1927411                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1774084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.017393                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               34117                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1364680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017393                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          34117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             1437080                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                 19.797170                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses            2067637                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.186251                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.385243                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                1901195                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     8655015000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.080499                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               166442                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     3981929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.037035                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                76575                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   6657680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.080499                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          166442                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3063000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.037035                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses           76575                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.204822                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.350671                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          6711.601001                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11490.800356                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.199945                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.368128                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.186251                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1901195                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    8655015000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.080499                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              166442                       # number of overall misses
+system.cpu.l2cache.overall_hits               1991062                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3981929500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.037035                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses               76575                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   6657680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.080499                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         166442                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3063000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.037035                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses          76575                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                 81066                       # number of replacements
-system.cpu.l2cache.sampled_refs                106133                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 49212                       # number of replacements
+system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18202.401357                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 2101133                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3296079                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   48460                       # number of writebacks
+system.cpu.l2cache.writebacks                   29460                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        757759238                       # number of cpu cycles simulated
+system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
 system.cpu.num_insts                        269696010                       # Number of instructions executed
 system.cpu.num_refs                         122219139                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             444                       # Number of system calls
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
index 003dd533c..77998b688 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
index 73953840b..063172b08 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:57:01
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:07:44
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -74,4 +72,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 745672616000 because target called exit()
+Exiting @ tick 719872424000 because target called exit()
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
index 24713e5f3..6c09813e2 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1125820                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214880                       # Number of bytes of host memory used
-host_seconds                                   496.95                       # Real time elapsed on the host
-host_tick_rate                             1500512692                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1404297                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200728                       # Number of bytes of host memory used
+host_seconds                                   398.40                       # Real time elapsed on the host
+host_tick_rate                             1806912378                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   559470527                       # Number of instructions simulated
-sim_seconds                                  0.745673                       # Number of seconds simulated
-sim_ticks                                745672616000                       # Number of ticks simulated
+sim_seconds                                  0.719872                       # Number of seconds simulated
+sim_ticks                                719872424000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          127326326                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20914.908888                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17914.908888                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 19806.811274                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16806.811274                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              126543330                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    16376290000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    15508654000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.006150                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               782996                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  14027302000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  13159666000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.006150                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          782996                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          55727847                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 53833.507889                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50833.507889                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              55072849                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   35260840000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.011754                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              654998                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  33295846000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011754                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         654998                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 28149.273084                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25149.273084                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              55371547                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   10029586000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.006394                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              356300                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   8960686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006394                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         356300                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 159.673059                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           183054173                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35909.141485                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 32909.141485                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               181616179                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     51637130000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.007856                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1437994                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 22415.807657                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19415.807657                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               181914877                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     25538240000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.006224                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1139296                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  47323148000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.007856                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1437994                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  22120352000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.006224                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1139296                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.992972                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4067.215006                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.992721                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4066.183353                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          183054173                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35909.141485                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 32909.141485                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 22415.807657                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19415.807657                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              181616179                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    51637130000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.007856                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1437994                       # number of overall misses
+system.cpu.dcache.overall_hits              181914877                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    25538240000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.006224                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1139296                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  47323148000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.007856                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1437994                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  22120352000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.006224                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1139296                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                1135200                       # number of replacements
 system.cpu.dcache.sampled_refs                1139296                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4067.215006                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4066.183353                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                181914877                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            11578483000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   808512                       # number of writebacks
+system.cpu.dcache.writebacks                  1025629                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses            11521                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.485313                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            993.921198                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.482234                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            987.615046                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          512145761                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   9788                       # number of replacements
 system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                993.921198                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                987.615046                       # Cycle average of tags in use
 system.cpu.icache.total_refs                512134240                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses          356300                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               33786                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  16770728000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.905175                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            322514                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  12900560000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.905175                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       322514                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              236267                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   6241716000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.336887                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            120033                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336887                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       120033                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            794517                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                662657                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    6856720000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.165962                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              131860                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   5274400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165962                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         131860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         298698                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51993.732800                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency  15530424000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           298698                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency  11947920000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       298698                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          808512                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              808512                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                683315                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    5782504000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.139962                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              111202                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4448080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139962                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         111202                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         1025629                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             1025629                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  4.737661                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.147006                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            1150817                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 696443                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    23627448000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.394827                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               454374                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 919582                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    12024220000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.200931                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               231235                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  18174960000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.394827                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          454374                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   9249400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.200931                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          231235                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.184240                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.380639                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          6037.178832                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12472.788257                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.178887                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.445562                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          5861.784368                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14600.161549                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           1150817                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                696443                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   23627448000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.394827                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              454374                       # number of overall misses
+system.cpu.l2cache.overall_hits                919582                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   12024220000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.200931                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              231235                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  18174960000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.394827                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         454374                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   9249400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.200931                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         231235                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                232496                       # number of replacements
-system.cpu.l2cache.sampled_refs                251560                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                212119                       # number of replacements
+system.cpu.l2cache.sampled_refs                232160                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18509.967089                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1191806                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          525324932000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  186433                       # number of writebacks
+system.cpu.l2cache.tagsinuse             20461.945917                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1427089                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          510281834000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                  172310                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1491345232                       # number of cpu cycles simulated
+system.cpu.numCycles                       1439744848                       # number of cpu cycles simulated
 system.cpu.num_insts                        559470527                       # Number of instructions executed
 system.cpu.num_refs                         184987503                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             548                       # Number of system calls
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
index 675fb37c6..086eb74a1 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -157,9 +157,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
index fb5635e2e..31b5a627d 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:20:12
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:22:00
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:23:05
+M5 executing on phenom
 command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -76,4 +74,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 1701783891000 because target called exit()
+Exiting @ tick 1658729604000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
index d803c2eef..c6740c4d4 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1040513                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213908                       # Number of bytes of host memory used
-host_seconds                                  1437.46                       # Real time elapsed on the host
-host_tick_rate                             1183878785                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1334580                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199248                       # Number of bytes of host memory used
+host_seconds                                  1120.73                       # Real time elapsed on the host
+host_tick_rate                             1480046497                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1495700521                       # Number of instructions simulated
-sim_seconds                                  1.701784                       # Number of seconds simulated
-sim_ticks                                1701783891000                       # Number of ticks simulated
+sim_seconds                                  1.658730                       # Number of seconds simulated
+sim_ticks                                1658729604000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          384102189                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 22845.361911                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19845.360753                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              382374775                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    39463398000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    38012508000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.004497                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1727414                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  34281154000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  32830264000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1727414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 53546.298194                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50546.298194                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             147974496                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   63490113500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.007949                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1185705                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  59932998500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.007949                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1185705                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             148369157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005303                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              791044                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005303                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         791044                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
@@ -37,50 +37,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           533262390                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35341.333979                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 32341.333293                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               530349271                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    102953511500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005463                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2913119                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               530743932                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.004723                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2518458                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  94214152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005463                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2913119                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.004723                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          2518458                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997733                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4086.713108                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4086.472055                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          533262390                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35341.333979                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 32341.333293                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              530349271                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   102953511500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005463                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2913119                       # number of overall misses
+system.cpu.dcache.overall_hits              530743932                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    59504521500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.004723                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2518458                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  94214152500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005463                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2913119                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.004723                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         2518458                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                2514362                       # number of replacements
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4086.713108                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4086.472055                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                530743932                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  1528950                       # number of writebacks
+system.cpu.dcache.writebacks                  2223170                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1068347110                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 48626.865672                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 48641.791045                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1068344296                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      136836000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      136878000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 2814                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    128394000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    128436000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            2814                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -92,31 +92,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1068347110                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 48626.865672                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45626.865672                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1068344296                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       136836000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       136878000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  2814                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    128394000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    128436000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.433486                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            887.780127                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            882.231489                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1068347110                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 48626.865672                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45626.865672                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1068344296                       # number of overall hits
-system.cpu.icache.overall_miss_latency      136836000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      136878000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 2814                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    128394000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    128436000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            2814                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -124,91 +124,82 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   1253                       # number of replacements
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                887.780127                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                882.231489                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1068344296                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses          791044                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.015933                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits               69270                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  37532259500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.912432                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            721774                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  28870960000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.912432                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       721774                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              543011                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.313551                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            248033                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.313551                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       248033                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           1730228                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               1364108                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   19038240000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.211602                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              366120                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  14644800000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.211602                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         366120                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         394661                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51994.993171                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency  20520396000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           394661                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency  15786440000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       394661                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         1528950                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             1528950                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               1398652                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   17241952000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.191637                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              331576                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  13263040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191637                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         331576                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             2223170                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.977137                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.351625                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses            2521272                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000.010571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.010352                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                1433378                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    56570499500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.431486                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1087894                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                1941663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    30139674000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.229888                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               579609                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  43515760000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.431486                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1087894                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  23184360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.229888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          579609                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.230883                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.374106                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          7565.560471                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12258.710159                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.230381                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.417452                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          7549.128601                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13679.064710                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           2521272                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000.010571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.010352                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               1433378                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   56570499500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.431486                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1087894                       # number of overall misses
+system.cpu.l2cache.overall_hits               1941663                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   30139674000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.229888                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              579609                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  43515760000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.431486                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1087894                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  23184360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.229888                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         579609                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                603454                       # number of replacements
-system.cpu.l2cache.sampled_refs                621473                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                568906                       # number of replacements
+system.cpu.l2cache.sampled_refs                587958                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             19824.270630                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 2471683                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          910963647000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  436481                       # number of writebacks
+system.cpu.l2cache.tagsinuse             21228.193311                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3146531                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          896565143000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                  411709                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3403567782                       # number of cpu cycles simulated
+system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
 system.cpu.num_insts                       1495700521                       # Number of instructions executed
 system.cpu.num_refs                         533262345                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             551                       # Number of system calls
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 23028a8af..3616ca38d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
index 6fdc0b7c3..614afa28e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:05
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:52
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,4 +16,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.133333
-Exiting @ tick 136571603500 because target called exit()
+Exiting @ tick 134780256500 because target called exit()
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 6e8eb7279..4907a0e08 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,339 +1,339 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 136199                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214028                       # Number of bytes of host memory used
-host_seconds                                  2757.55                       # Real time elapsed on the host
-host_tick_rate                               49526494                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 209084                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200220                       # Number of bytes of host memory used
+host_seconds                                  1796.28                       # Real time elapsed on the host
+host_tick_rate                               75032789                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   375574819                       # Number of instructions simulated
-sim_seconds                                  0.136572                       # Number of seconds simulated
-sim_ticks                                136571603500                       # Number of ticks simulated
+sim_seconds                                  0.134780                       # Number of seconds simulated
+sim_ticks                                134780256500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 34712245                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              43971564                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                1375                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            5750083                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           35466067                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 62830534                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 12729193                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits                 34013245                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              43763729                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                1420                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect            5537198                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           35178330                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 62077463                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 12488414                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               44587532                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          12727499                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events          13095097                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples    257005436                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.551191                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.213326                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples    254238271                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.568075                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.238705                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    123174402     47.93%     47.93% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     51601116     20.08%     68.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2     20452287      7.96%     75.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     20740884      8.07%     84.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     11122877      4.33%     88.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      8764041      3.41%     91.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      5151763      2.00%     93.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7      3270567      1.27%     95.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     12727499      4.95%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    122261214     48.09%     48.09% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     50419868     19.83%     67.92% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2     19851999      7.81%     75.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     19999442      7.87%     83.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     10886968      4.28%     87.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      9291241      3.65%     91.53% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6      5249545      2.06%     93.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7      3182897      1.25%     94.85% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     13095097      5.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total    257005436                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total    254238271                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                 398664594                       # Number of instructions committed
 system.cpu.commit.COM:loads                 100651995                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  174183397                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           5745758                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts           5532855                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts      398664594                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        99827575                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        94873241                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                   375574819                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             375574819                       # Number of Instructions Simulated
-system.cpu.cpi                               0.727267                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.727267                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.717728                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.717728                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           95959241                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33093.582888                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31984.199796                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               95957558                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       55696500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                 1683                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits               702                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     31376500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_accesses           95565604                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33374.015748                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31987.257900                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               95563953                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       55100500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                 1651                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits               670                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency     31379500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             981                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 30331.836439                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36071.185392                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              73502803                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     543728500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000244                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               17926                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits            14695                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency    116546000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           3231                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 30116.133558                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35471.048513                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              73502909                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     536669500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000242                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               17820                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits            14625                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency    113330000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           3195                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               40579.607280                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               40485.360393                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           169479970                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30568.871437                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35119.301994                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               169460361                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       599425000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000116                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                 19609                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits              15397                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    147922500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses           169086333                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30392.378409                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34652.658046                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               169066862                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       591770000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000115                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                 19471                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits              15295                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency    144709500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4212                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4176                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.804256                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3294.233360                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          169479970                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30568.871437                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35119.301994                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.804225                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           3294.106020                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          169086333                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30392.378409                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34652.658046                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              169460361                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      599425000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000116                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                19609                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits             15397                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    147922500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits              169066862                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      591770000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000115                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                19471                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits             15295                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency    144709500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4212                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4176                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    781                       # number of replacements
 system.cpu.dcache.sampled_refs                   4176                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3294.233360                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                169460440                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3294.106020                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                169066865                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      638                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       21059081                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred           4405                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      11508131                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       539100093                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         134649980                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          100169012                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        15996729                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          13181                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1127363                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                185557278                       # DTB accesses
+system.cpu.dcache.writebacks                      662                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       22152007                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred           4419                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      11286796                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       532040738                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         132274950                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           98625859                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        15181213                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts          13245                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1185455                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                184734537                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    185509117                       # DTB hits
-system.cpu.dtb.data_misses                      48161                       # DTB misses
+system.cpu.dtb.data_hits                    184683089                       # DTB hits
+system.cpu.dtb.data_misses                      51448                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                105313060                       # DTB read accesses
+system.cpu.dtb.read_accesses                104442295                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    105266355                       # DTB read hits
-system.cpu.dtb.read_misses                      46705                       # DTB read misses
-system.cpu.dtb.write_accesses                80244218                       # DTB write accesses
+system.cpu.dtb.read_hits                    104392308                       # DTB read hits
+system.cpu.dtb.read_misses                      49987                       # DTB read misses
+system.cpu.dtb.write_accesses                80292242                       # DTB write accesses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                    80242762                       # DTB write hits
-system.cpu.dtb.write_misses                      1456                       # DTB write misses
-system.cpu.fetch.Branches                    62830534                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  64860863                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     168703371                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               1410406                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      552550587                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                 6169479                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.230028                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           64860863                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           47441438                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.022934                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples          273002165                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.023979                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.024544                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits                    80290781                       # DTB write hits
+system.cpu.dtb.write_misses                      1461                       # DTB write misses
+system.cpu.fetch.Branches                    62077463                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  63755206                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     165857748                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               1527822                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      544006695                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                 5884776                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.230291                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           63755206                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           46501659                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        2.018125                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples          269419484                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.019181                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.021968                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                169159964     61.96%     61.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 10172385      3.73%     65.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 10846224      3.97%     69.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  7014396      2.57%     72.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 14631841      5.36%     77.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  9961062      3.65%     81.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  7189550      2.63%     83.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4041352      1.48%     85.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 39985391     14.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                167317249     62.10%     62.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  9830332      3.65%     65.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 10264297      3.81%     69.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  7467850      2.77%     72.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 14528793      5.39%     77.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  9632139      3.58%     81.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7095921      2.63%     83.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3870398      1.44%     85.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 39412505     14.63%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            273002165                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses           64860863                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 32283.674736                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 30878.201844                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               64856030                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      156027000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000075                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 4833                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               929                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    120548500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000060                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            3904                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total            269419484                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses           63755206                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 32282.788581                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30880.348450                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               63750372                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      156055000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000076                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                 4834                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               931                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    120526000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses            3903                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               16612.712602                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               16333.684858                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            64860863                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 32283.674736                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 30878.201844                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                64856030                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       156027000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000075                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  4833                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                929                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    120548500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000060                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             3904                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            63755206                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 32282.788581                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30880.348450                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                63750372                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       156055000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000076                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                  4834                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                931                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    120526000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses             3903                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.891431                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1825.650576                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           64860863                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 32283.674736                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 30878.201844                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.891530                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1825.852920                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           63755206                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 32282.788581                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30880.348450                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               64856030                       # number of overall hits
-system.cpu.icache.overall_miss_latency      156027000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000075                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 4833                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               929                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    120548500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000060                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            3904                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               63750372                       # number of overall hits
+system.cpu.icache.overall_miss_latency      156055000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000076                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                 4834                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               931                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    120526000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses            3903                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   1982                       # number of replacements
-system.cpu.icache.sampled_refs                   3904                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   1981                       # number of replacements
+system.cpu.icache.sampled_refs                   3903                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1825.650576                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 64856030                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1825.852920                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 63750372                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          141045                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 51385726                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      27755438                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.545021                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    192526473                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   80254900                       # Number of stores executed
+system.cpu.idleCycles                          141032                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 50928648                       # Number of branches executed
+system.cpu.iew.EXEC:nop                      27198310                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.554098                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    191466035                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   80302922                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                 290066917                       # num instructions consuming a value
-system.cpu.iew.WB:count                     417830932                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.699779                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                 288648946                       # num instructions consuming a value
+system.cpu.iew.WB:count                     415155943                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.699341                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                 202982772                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.529714                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      418648136                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              6175903                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 3284723                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             125889658                       # Number of dispatched load instructions
+system.cpu.iew.WB:producers                 201863998                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.540121                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      415846665                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              6072161                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 3214599                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             125039862                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                241                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           6874932                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             92903281                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           498492595                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             112271573                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9215998                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             422011987                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 145222                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts           6489838                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             92505583                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           493538259                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             111163113                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           8697897                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             418923368                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 138014                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 28045                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               15996729                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                550279                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 28455                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               15181213                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                561595                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads         9131244                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         2248                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads         8650010                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses        47350                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       648565                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads       175867                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     25237663                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     19371879                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         648565                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      1211280                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        4964623                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.375011                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.375011                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       540044                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads       176691                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     24387867                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     18974181                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         540044                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      1086448                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        4985713                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.393286                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.393286                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass        33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu       168382264     39.05%     39.05% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult        2152290      0.50%     39.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     39.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd      34830384      8.08%     47.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp       7781044      1.80%     49.44% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2959993      0.69%     50.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult     16854742      3.91%     54.03% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv       1589897      0.37%     54.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     54.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      114726286     26.60%     81.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      81917504     19.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu       166094034     38.84%     38.85% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult        2150895      0.50%     39.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     39.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd      34767843      8.13%     47.48% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp       7837636      1.83%     49.32% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2956341      0.69%     50.01% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult     16811834      3.93%     53.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv       1571362      0.37%     54.31% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     54.31% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      113187864     26.47%     80.78% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      82209875     19.22%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        431227985                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               9397735                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.021793                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        427621265                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               9425623                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.022042                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             51470      0.55%      0.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd           51324      0.55%      1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp            3037      0.03%      1.13% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt            5843      0.06%      1.19% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult        1281381     13.63%     14.82% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv          969484     10.32%     25.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     25.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          5699185     60.64%     85.78% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         1336011     14.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             22465      0.24%      0.24% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.24% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.24% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd           44257      0.47%      0.71% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp             507      0.01%      0.71% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt            7079      0.08%      0.79% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult        1310742     13.91%     14.69% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv         1081807     11.48%     26.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     26.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          5661778     60.07%     86.24% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite         1296988     13.76%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples    273002165                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.579577                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.704793                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples    269419484                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.587195                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.714658                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     100185843     36.70%     36.70% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      58377873     21.38%     58.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      43478311     15.93%     74.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3      28530639     10.45%     84.46% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      23283249      8.53%     92.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      11208488      4.11%     97.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       5200545      1.90%     99.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       1974869      0.72%     99.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        762348      0.28%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      98807587     36.67%     36.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      58261038     21.62%     58.30% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      40917124     15.19%     73.49% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3      29020181     10.77%     84.26% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      23205890      8.61%     92.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      11236315      4.17%     97.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       5001720      1.86%     98.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7       2307051      0.86%     99.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        662578      0.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total    273002165                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.578762                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                  470736916                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 431227985                       # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total    269419484                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.586365                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                  466339708                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 427621265                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 241                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        94399417                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            779543                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        89739850                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            704910                       # Number of squashed instructions issued
 system.cpu.iq.iqSquashedNonSpecRemoved             26                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     72495736                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined     69710487                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                64861170                       # ITB accesses
+system.cpu.itb.fetch_accesses                63755513                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    64860863                       # ITB hits
+system.cpu.itb.fetch_hits                    63755206                       # ITB hits
 system.cpu.itb.fetch_misses                       307                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,106 +344,97 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            3199                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.066333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31448.372966                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    110511500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999062                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              3196                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    100509000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999062                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         3196                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses              4881                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34355.892097                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31170.255561                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34585.272553                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31456.646478                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                  62                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    108494000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.980619                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              3137                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     98679500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.980619                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         3137                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses              4880                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34357.396450                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.467456                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                   655                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     145188000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.865806                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                4226                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    131725500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.865806                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           4226                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             36                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34236.111111                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      1232500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               36                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1116000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           36                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             638                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 638                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_miss_latency     145160000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.865779                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                4225                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    131691000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.865779                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           4225                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses             662                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 662                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.134782                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.152443                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses               8080                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34451.562921                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31290.016168                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                    658                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      255699500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.918564                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7422                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses               8079                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34454.496061                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.836457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                    717                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      253654000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.911251                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 7362                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    232234500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.918564                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7422                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    230370500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.911251                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            7362                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.108617                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011284                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3559.151087                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           369.756870                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses              8080                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34451.562921                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31290.016168                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.108627                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.011574                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3559.477751                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           379.255991                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses              8079                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34454.496061                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.836457                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                   658                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     255699500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.918564                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7422                       # number of overall misses
+system.cpu.l2cache.overall_hits                   717                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     253654000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.911251                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                7362                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    232234500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.918564                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7422                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    230370500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.911251                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           7362                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    14                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4741                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                    13                       # number of replacements
+system.cpu.l2cache.sampled_refs                  4769                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3928.907957                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     639                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3938.733742                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     727                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          73373175                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         55113413                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            125889658                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            92903281                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                        273143210                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         10612512                       # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads          72822522                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         52763057                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            125039862                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            92505583                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                        269560516                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         11010620                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         2173514                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         139438532                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        7156113                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IQFullEvents         2256823                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         137290050                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        7674469                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      690877715                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       524876259                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    339660686                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           96195896                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        15996729                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       10389927                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          80128345                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles       368569                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts        37570                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           22417777                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          259                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                            3102                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups      683176131                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       518444566                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    335488186                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           94400681                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        15181213                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       11169785                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          75955845                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles       367135                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts        37569                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           24308277                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts          261                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                            3095                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 059f841f0..73f05f718 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
index 497d4cb17..13f02bc2e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:05
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:42:55
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,4 +16,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.566667
-Exiting @ tick 567347489000 because target called exit()
+Exiting @ tick 567343170000 because target called exit()
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 576c22b47..137741cba 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1188061                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213244                       # Number of bytes of host memory used
-host_seconds                                   335.56                       # Real time elapsed on the host
-host_tick_rate                             1690751695                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1240949                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199424                       # Number of bytes of host memory used
+host_seconds                                   321.26                       # Real time elapsed on the host
+host_tick_rate                             1766004728                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   398664609                       # Number of instructions simulated
-sim_seconds                                  0.567347                       # Number of seconds simulated
-sim_ticks                                567347489000                       # Number of ticks simulated
+sim_seconds                                  0.567343                       # Number of seconds simulated
+sim_ticks                                567343170000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
@@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       #
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55961.075070                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52961.075070                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              73517493                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     181146000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     176792000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                3237                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    171435000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency    167186000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           3237                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54796.274182                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51796.274182                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               168271033                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       229432000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       225078000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4187                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    216871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    212622000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4187                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.802957                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3288.911680                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54796.274182                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51796.274182                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              168271033                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      229432000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              168271068                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      225078000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4187                       # number of overall misses
+system.cpu.dcache.overall_misses                 4152                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    216871000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    212622000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4187                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3288.911680                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      625                       # number of writebacks
+system.cpu.dcache.writebacks                      649                       # number of writebacks
 system.cpu.dtb.data_accesses                168275276                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    168275220                       # DTB hits
@@ -122,7 +122,7 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.876529                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1795.130856                       # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   1769                       # number of replacements
 system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1795.130856                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1795.131074                       # Cycle average of tags in use
 system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,13 +164,13 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    166348000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999063                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              3199                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    127960000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999063                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         3199                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    163384000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              3142                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    125680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981262                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         3142                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
@@ -181,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses                4038                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             35                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      1820000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               35                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1400000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           35                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             625                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 625                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.125220                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.143482                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                    588                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      376324000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.924856                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 7237                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                    645                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      373360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.917572                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 7180                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    289480000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.924856                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            7237                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    287200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.917572                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            7180                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.103673                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.011078                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3397.172145                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           362.997313                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.103674                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.011338                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                   588                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     376324000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.924856                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                7237                       # number of overall misses
+system.cpu.l2cache.overall_hits                   645                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     373360000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.917572                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                7180                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    289480000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.924856                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           7237                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    287200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.917572                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           7180                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                    14                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4544                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                    13                       # number of replacements
+system.cpu.l2cache.sampled_refs                  4572                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3760.169458                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     569                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     656                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1134694978                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
 system.cpu.num_insts                        398664609                       # Number of instructions executed
 system.cpu.num_refs                         174183455                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
index 9a41cf5e7..ff00126d1 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
index 13d544b5b..691b24bb3 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:52:33
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:12:46
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -20,4 +18,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.520000
-Exiting @ tick 525827779000 because target called exit()
+Exiting @ tick 525825884000 because target called exit()
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
index ac525a38a..0a058648f 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 898977                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219380                       # Number of bytes of host memory used
-host_seconds                                   383.10                       # Real time elapsed on the host
-host_tick_rate                             1372552338                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1114146                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 205224                       # Number of bytes of host memory used
+host_seconds                                   309.12                       # Real time elapsed on the host
+host_tick_rate                             1701065680                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   344399678                       # Number of instructions simulated
-sim_seconds                                  0.525828                       # Number of seconds simulated
-sim_ticks                                525827779000                       # Number of ticks simulated
+sim_seconds                                  0.525826                       # Number of seconds simulated
+sim_ticks                                525825884000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           94586725                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439                       # average ReadReq mshr miss latency
@@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency     75091000                       #
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses            1607                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          82063572                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              82060677                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     162078000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              82060700                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                2895                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    153393000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency    151544000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           2895                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               39438.673365                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           176650297                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53751.665926                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               176645795                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       241990000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 53599.464166                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 50599.464166                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               176645818                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       240072000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  4502                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  4479                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    228484000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    226635000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             4502                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             4479                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.751814                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           3079.430321                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           3079.431639                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          176650297                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53751.665926                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 53599.464166                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 50599.464166                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              176645795                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      241990000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits              176645818                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      240072000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 4502                       # number of overall misses
+system.cpu.dcache.overall_misses                 4479                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    228484000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    226635000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            4502                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            4479                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                   1332                       # number of replacements
 system.cpu.dcache.sampled_refs                   4479                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               3079.430321                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3079.431639                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                176645818                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      974                       # number of writebacks
+system.cpu.dcache.writebacks                      998                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -115,7 +115,7 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.862305                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1766.000778                       # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0           1766.001397                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          348627536                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  13796                       # number of replacements
 system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1766.000778                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1766.001397                       # Cycle average of tags in use
 system.cpu.icache.total_refs                348611933                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,13 +150,13 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses            2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   1                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency    149292000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999652                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              2871                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    114840000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999652                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         2871                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                  16                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency    148512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              2856                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses             17210                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
@@ -167,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses                3977                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231087                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             23                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency      1196000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               23                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       920000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           23                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             974                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 974                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses             998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.717391                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.725579                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses              20082                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  13234                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      356096000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.341002                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 6848                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  13249                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.340255                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    273920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.341002                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            6848                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    273320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.340255                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.095645                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.010365                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3134.105136                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           339.639233                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::1                  0.010426                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3134.106018                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           341.623002                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             20082                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 13234                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     356096000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.341002                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                6848                       # number of overall misses
+system.cpu.l2cache.overall_hits                 13249                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.340255                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                6833                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    273920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.341002                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           6848                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.340255                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                    48                       # number of replacements
-system.cpu.l2cache.sampled_refs                  4876                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              3473.744369                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13250                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3475.729020                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13309                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1051655558                       # number of cpu cycles simulated
+system.cpu.numCycles                       1051651768                       # number of cpu cycles simulated
 system.cpu.num_insts                        344399678                       # Number of instructions executed
 system.cpu.num_refs                         177028576                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             191                       # Number of system calls
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 74dda4fbe..eac5f120d 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index e4a42f3b8..3c7b7367e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:01:20
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:48:50
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 702688811500 because target called exit()
+Exiting @ tick 702197148500 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 75ed9ac65..24cbff05f 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,295 +1,295 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 105247                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214344                       # Number of bytes of host memory used
-host_seconds                                 17321.56                       # Real time elapsed on the host
-host_tick_rate                               40567294                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 211797                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200548                       # Number of bytes of host memory used
+host_seconds                                  8607.50                       # Real time elapsed on the host
+host_tick_rate                               81579716                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1823043370                       # Number of instructions simulated
-sim_seconds                                  0.702689                       # Number of seconds simulated
-sim_ticks                                702688811500                       # Number of ticks simulated
+sim_seconds                                  0.702197                       # Number of seconds simulated
+sim_ticks                                702197148500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                239396241                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             292393914                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                3599                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           28358143                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          232710596                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                347019771                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 49329086                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits                239361289                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             292350506                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 817                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           28355767                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          232672074                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                346972918                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 49326443                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches              266706457                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          67430429                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events          67076252                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1305107182                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.539328                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.193562                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples   1304193061                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.540407                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.191824                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    596079504     45.67%     45.67% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    274005611     20.99%     66.67% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    176024939     13.49%     80.16% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     67867193      5.20%     85.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     46132467      3.53%     88.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     33942844      2.60%     91.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     19726349      1.51%     93.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     23897846      1.83%     94.83% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     67430429      5.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    594441372     45.58%     45.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    274309752     21.03%     66.61% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2    176336103     13.52%     80.13% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     68165188      5.23%     85.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     46116026      3.54%     88.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     34003883      2.61%     91.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     19794848      1.52%     93.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7     23949637      1.84%     94.86% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     67076252      5.14%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1305107182                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total   1304193061                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                2008987604                       # Number of instructions committed
 system.cpu.commit.COM:loads                 511595302                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  722390433                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          28346322                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts          28343948                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       694586134                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       694286197                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
-system.cpu.cpi                               0.770896                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.770896                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses            8                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits                8                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses          463358852                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34710.185206                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              461425148                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    72449480000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.004173                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1933704                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            474303                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  50656079000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.003150                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1459401                       # number of ReadReq MSHR misses
+system.cpu.cpi                               0.770357                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.770357                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses            9                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses          463422916                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 37046.413098                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34119.469160                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              461494441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    71443081500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.004161                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1928475                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            469203                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  49789586000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003149                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1459272                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             210236618                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   21543675991                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.002648                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              558278                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           484005                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   2712773000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000352                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          74273                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 37873.224315                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34361.981856                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             210247567                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   20729113991                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.002597                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              547329                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits           475679                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   2462036000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000340                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          71650                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs  6041.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        14500                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 438.700297                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 438.782653                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs        72500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        14500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           674153748                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 37718.232311                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               671661766                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     93993155991                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003696                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2491982                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             958308                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  53368852000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002275                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1533674                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           674217812                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 37229.197259                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34130.819206                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               671742008                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     92172195491                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.003672                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2475804                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits             944882                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  52251622000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002271                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1530922                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999781                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4095.104320                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          674153748                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 37718.232311                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826                       # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0           4095.103693                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          674217812                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 37229.197259                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34130.819206                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              671661766                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    93993155991                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003696                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2491982                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            958308                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  53368852000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002275                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1533674                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              671742008                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    92172195491                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.003672                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2475804                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits            944882                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  52251622000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002271                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1530922                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1526954                       # number of replacements
-system.cpu.dcache.sampled_refs                1531050                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1526826                       # number of replacements
+system.cpu.dcache.sampled_refs                1530922                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.104320                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                671672090                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4095.103693                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                671742017                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              274011000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    74616                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       31207203                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          12052                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      30419221                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      2934529925                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         711825403                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          561989361                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles       100109049                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts          45710                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles          85215                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                772921338                       # DTB accesses
+system.cpu.dcache.writebacks                   107349                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       30546765                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          11879                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      30415983                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      2934070840                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         711662273                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          561899990                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles       100055757                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts          45705                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles          84033                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                772892535                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    772287215                       # DTB hits
-system.cpu.dtb.data_misses                     634123                       # DTB misses
+system.cpu.dtb.data_hits                    772261224                       # DTB hits
+system.cpu.dtb.data_misses                     631311                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                514592222                       # DTB read accesses
+system.cpu.dtb.read_accesses                514571381                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    513995856                       # DTB read hits
-system.cpu.dtb.read_misses                     596366                       # DTB read misses
-system.cpu.dtb.write_accesses               258329116                       # DTB write accesses
+system.cpu.dtb.read_hits                    513977951                       # DTB read hits
+system.cpu.dtb.read_misses                     593430                       # DTB read misses
+system.cpu.dtb.write_accesses               258321154                       # DTB write accesses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                   258291359                       # DTB write hits
-system.cpu.dtb.write_misses                     37757                       # DTB write misses
-system.cpu.fetch.Branches                   347019771                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 347236210                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     925540339                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               4572630                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     3016868050                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                28795074                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.246923                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          347236210                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          288725327                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.146660                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1405216231                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.146907                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.027321                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits                   258283273                       # DTB write hits
+system.cpu.dtb.write_misses                     37881                       # DTB write misses
+system.cpu.fetch.Branches                   346972918                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 347200626                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     925414333                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               4548226                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     3016464690                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                28792576                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.247062                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          347200626                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          288687732                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        2.147876                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples         1404248818                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.148098                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.027750                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                826912311     58.85%     58.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 54085812      3.85%     62.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 40125133      2.86%     65.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 63577185      4.52%     70.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                121409089      8.64%     78.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 34600240      2.46%     81.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 37932193      2.70%     83.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7024441      0.50%     84.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                219549827     15.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                826035319     58.82%     58.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 54061013      3.85%     62.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 40121660      2.86%     65.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 63576700      4.53%     70.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                121382183      8.64%     78.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 34599008      2.46%     81.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 37926839      2.70%     83.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7023317      0.50%     84.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                219522779     15.63%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1405216231                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses          347236210                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15852.092893                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.295350                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              347225531                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      169284500                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total           1404248818                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses          347200626                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15854.453498                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.008587                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              347189949                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      169278000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000031                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                10679                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               894                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    113959000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                10677                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               895                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    113843000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000028                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses            9785                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses            9782                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               35489.118050                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               35496.365300                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           347236210                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15852.092893                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               347225531                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       169284500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses           347200626                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15854.453498                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11638.008587                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               347189949                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       169278000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000031                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 10679                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                894                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    113959000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                 10677                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                895                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    113843000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000028                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses             9785                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses             9782                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.787162                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1612.107078                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          347236210                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15852.092893                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11646.295350                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.787157                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1612.097956                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          347200626                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15854.453498                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11638.008587                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              347225531                       # number of overall hits
-system.cpu.icache.overall_miss_latency      169284500                       # number of overall miss cycles
+system.cpu.icache.overall_hits              347189949                       # number of overall hits
+system.cpu.icache.overall_miss_latency      169278000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000031                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                10679                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               894                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    113959000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                10677                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               895                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    113843000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses            9785                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses            9782                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   8113                       # number of replacements
-system.cpu.icache.sampled_refs                   9784                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   8111                       # number of replacements
+system.cpu.icache.sampled_refs                   9781                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1612.107078                       # Cycle average of tags in use
-system.cpu.icache.total_refs                347225531                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1612.097956                       # Cycle average of tags in use
+system.cpu.icache.total_refs                347189949                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          161393                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                274718833                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     329034713                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.424505                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    773457001                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  258330075                       # Number of stores executed
+system.cpu.idleCycles                          145480                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                274684945                       # Number of branches executed
+system.cpu.iew.EXEC:nop                     329038670                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.425383                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    773428063                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  258322146                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1632862772                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2000954749                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.695811                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                1632528882                       # num instructions consuming a value
+system.cpu.iew.WB:count                    2000778402                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.695828                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1136164328                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.423784                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2001905607                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             30878599                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 3451748                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             655963109                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 64                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts             51733                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            302851236                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2713712461                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             515126926                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          84126603                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2001967300                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 131046                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                1135959868                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.424656                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     2001740023                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             30875630                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 3371474                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             655915316                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 69                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts             46568                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            302840686                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          2713549765                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             515105917                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          84189444                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            2001799378                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 130178                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  1380                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles              100109049                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                140868                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  1349                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              100055757                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                139189                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked           16                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        50632865                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses          227                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads        50550937                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses          225                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation         3782                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         4125                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    144367807                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     92056105                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents           3782                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       787958                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       30090641                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.297191                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.297191                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation         3543                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads         4083                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    144320014                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     92045555                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents           3543                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       788016                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       30087614                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.298099                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.298099                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass         2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1203926458     57.71%     57.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          17656      0.00%     57.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu      1203839026     57.71%     57.71% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          18400      0.00%     57.71% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     57.71% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd      27851408      1.34%     59.05% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp       8254704      0.40%     59.44% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       7204646      0.35%     59.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd      27850839      1.34%     59.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp       8254698      0.40%     59.44% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt       7204647      0.35%     59.79% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatMult            4      0.00%     59.79% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     59.79% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     59.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      555703221     26.64%     86.43% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     283133054     13.57%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      555691648     26.64%     86.43% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite     283126808     13.57%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2086093903                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              35524455                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.017029                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total       2085988822                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt              36673966                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.017581                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu              5029      0.01%      0.01% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu              5496      0.01%      0.01% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.01% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.01% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.01% # attempts to use FU when none available
@@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.01% # at
 system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.01% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.01% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.01% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead         26764066     75.34%     75.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         8755360     24.65%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead         27909398     76.10%     76.12% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite         8759072     23.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1405216231                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.484536                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.637275                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1404248818                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.485484                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.638010                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     532926303     37.92%     37.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     283749414     20.19%     58.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     275573113     19.61%     77.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     156459284     11.13%     88.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4      63140415      4.49%     93.36% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      47210297      3.36%     96.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      32913048      2.34%     99.06% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7      10225878      0.73%     99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       3018479      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     532242124     37.90%     37.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     283422756     20.18%     58.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     275702525     19.63%     77.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3     156569721     11.15%     88.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4      62891882      4.48%     93.35% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      46986104      3.35%     96.69% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6      33054153      2.35%     99.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7      10407537      0.74%     99.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8       2972016      0.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1405216231                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.484365                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                 2384677684                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                2086093903                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  64                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       561606840                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued          12399741                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             25                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    517624785                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total   1404248818                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.485330                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                 2384511026                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                2085988822                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  69                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       561440182                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued          12400568                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             30                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined    517571269                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               347236419                       # ITB accesses
+system.cpu.itb.fetch_accesses               347200834                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   347236210                       # ITB hits
-system.cpu.itb.fetch_misses                       209                       # ITB misses
+system.cpu.itb.fetch_hits                   347200626                       # ITB hits
+system.cpu.itb.fetch_misses                       208                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -343,106 +343,98 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_acv                            0                       # DTB write access violations
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses           71649                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   2514267000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             71649                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2297462000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        71649                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           1469186                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 29045                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   49263470000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.980231                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1440141                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  44644985000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.980231                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1440141                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           2624                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency     89995000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             2624                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency     81349000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         2624                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           74616                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               74616                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_accesses           71650                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 35152.205453                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32141.578294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                4793                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   2350171000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.933105                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             66857                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2148889500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.933105                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        66857                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           1469054                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34210.498210                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.429333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 55232                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   48367555000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.962403                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1413822                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43829089000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.962403                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1413822                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          107349                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              107349                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7200                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.023753                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.041538                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs        36000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1540835                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34249.291899                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  29045                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    51777737000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.981150                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1511790                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses            1540704                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34253.019054                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.955556                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  60025                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    50717726000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.961041                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1480679                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  46942447000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.981150                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1511790                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  45977978500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.961041                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1480679                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.927958                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.046323                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         30407.323461                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          1517.897239                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           1540835                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34249.291899                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.881669                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.093123                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         28890.531626                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3051.454384                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           1540704                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34253.019054                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.955556                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 29045                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   51777737000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.981150                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1511790                       # number of overall misses
+system.cpu.l2cache.overall_hits                 60025                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   50717726000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.961041                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1480679                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  46942447000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.981150                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1511790                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  45977978500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.961041                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1480679                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1474292                       # number of replacements
-system.cpu.l2cache.sampled_refs               1506959                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1480409                       # number of replacements
+system.cpu.l2cache.sampled_refs               1513096                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31925.220700                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   35795                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             31941.986010                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   62851                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66899                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         126385471                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         12290638                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            655963109                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           302851236                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                       1405377624                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         20016233                       # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks                   66898                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         122494554                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         20280761                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            655915316                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           302840686                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                       1404394298                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         19598244                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1384969070                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents          673555                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         725805122                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       10749358                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             18                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     3307765426                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2838518766                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   1890285688                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          546657671                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles       100109049                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       12606278                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         505316618                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles        21878                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         2883                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           26993135                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts           69                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                            4180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents          671773                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         725577995                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       10516920                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents             17                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     3307285723                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      2838114179                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   1889955714                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          546658925                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles       100055757                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       12336225                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps         504986644                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles        21672                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts         2827                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           26425102                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts           76                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                            3680                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 1ed5d3e81..9457f21b2 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 384b357fd..c8bf5015e 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:14
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:48:17
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 2814926000000 because target called exit()
+Exiting @ tick 2813467842000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index bd497ee51..21606e309 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1265087                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213100                       # Number of bytes of host memory used
-host_seconds                                  1588.02                       # Real time elapsed on the host
-host_tick_rate                             1772597573                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1340007                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 199308                       # Number of bytes of host memory used
+host_seconds                                  1499.24                       # Real time elapsed on the host
+host_tick_rate                             1876600376                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  2008987605                       # Number of instructions simulated
-sim_seconds                                  2.814926                       # Number of seconds simulated
-sim_ticks                                2814926000000                       # Number of ticks simulated
+sim_seconds                                  2.813468                       # Number of seconds simulated
+sim_ticks                                2813467842000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55392.203496                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.203496                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    80772468000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    79658418000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  76397892000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  75283842000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             210720566                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    4162480000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000353                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               74330                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   3939490000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          74330                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55421.682690                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52421.682690                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               720332400                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     84934948000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002123                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1532522                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  80337382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002123                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1532522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4095.205038                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           4095.204626                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55421.682690                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52421.682690                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              720332400                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    84934948000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002123                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1532522                       # number of overall misses
+system.cpu.dcache.overall_hits              720334778                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    83474412000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1530144                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  80337382000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002123                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1532522                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                1526048                       # number of replacements
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.205038                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.204626                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1049839000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    74616                       # number of writebacks
+system.cpu.dcache.writebacks                   107612                       # number of writebacks
 system.cpu.dtb.data_accesses                722298387                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    721864922                       # DTB hits
@@ -122,7 +122,7 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.721886                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1478.422015                       # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0           1478.423269                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   9046                       # number of replacements
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1478.422015                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1478.423269                       # Cycle average of tags in use
 system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,36 +164,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency   3741504000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             71952                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2878080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        71952                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                5079                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.929411                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             66873                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.929411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        66873                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 29321                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   74852284000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.980037                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1439467                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  57578680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.980037                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1439467                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           2378                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    123656000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             2378                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency     95120000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         2378                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           74616                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               74616                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                 55846                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   73472984000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.961978                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1412942                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56517680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961978                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1412942                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              107612                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.023963                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.041938                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  29321                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    78593788000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.980970                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1511419                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  60925                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    76950380000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.960457                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1479815                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  60456760000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.980970                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1511419                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  59192600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.960457                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1479815                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.927128                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.046829                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         30380.118149                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          1534.487101                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.880371                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.094050                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         28848.012979                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3081.828747                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 29321                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   78593788000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.980970                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1511419                       # number of overall misses
+system.cpu.l2cache.overall_hits                 60925                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   76950380000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.960457                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1479815                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  60456760000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.980970                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1511419                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  59192600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.960457                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1479815                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1473631                       # number of replacements
-system.cpu.l2cache.sampled_refs               1506296                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1479797                       # number of replacements
+system.cpu.l2cache.sampled_refs               1512480                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31914.605250                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   36095                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             31929.841726                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   63431                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66899                       # number of writebacks
+system.cpu.l2cache.writebacks                   66898                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       5629852000                       # number of cpu cycles simulated
+system.cpu.numCycles                       5626935684                       # number of cpu cycles simulated
 system.cpu.num_insts                       2008987605                       # Number of instructions executed
 system.cpu.num_refs                         722823898                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 3cf240e1d..5d6a2ea44 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
index 8e18e8ced..6d3d29284 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 14:03:19
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:06:09
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1392,4 +1390,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 2371349716000 because target called exit()
+Exiting @ tick 2369896178000 because target called exit()
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index be056051b..bc599ef4c 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1110314                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216744                       # Number of bytes of host memory used
-host_seconds                                  1650.59                       # Real time elapsed on the host
-host_tick_rate                             1436666087                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1326917                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202424                       # Number of bytes of host memory used
+host_seconds                                  1381.15                       # Real time elapsed on the host
+host_tick_rate                             1715881736                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1832675505                       # Number of instructions simulated
-sim_seconds                                  2.371350                       # Number of seconds simulated
-sim_ticks                                2371349716000                       # Number of ticks simulated
+sim_seconds                                  2.369896                       # Number of seconds simulated
+sim_ticks                                2369896178000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          620364065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55313.730657                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.730657                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              618902904                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    80822266000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency    79731778000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              1461161                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  76438783000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  75348295000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         1461161                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         276945663                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.434541                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.434541                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             276871387                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    4159414000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               74276                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   3936586000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000268                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          74276                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             276872883                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 583.970170                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           897309728                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55346.901240                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52346.901240                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               895774291                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     84981680000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.001711                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1535437                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 54452.292494                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               895775787                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     83526604000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1533941                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  80375369000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.001711                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1535437                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  78924781000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1533941                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999748                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4094.966832                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           4094.966269                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          897309728                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55346.901240                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52346.901240                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54452.292494                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              895774291                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    84981680000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.001711                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1535437                       # number of overall misses
+system.cpu.dcache.overall_hits              895775787                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    83526604000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1533941                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  80375369000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.001711                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1535437                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency  78924781000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1533941                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                1529845                       # number of replacements
 system.cpu.dcache.sampled_refs                1533941                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.966832                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.966269                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                895775787                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              993999000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    74582                       # number of writebacks
+system.cpu.dcache.warmup_cycle              993944000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   107259                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses                       0                       # DT
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
 system.cpu.icache.ReadReq_accesses         1390241555                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18784.729586                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15784.729586                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1390221752                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      371994000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      372036000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    312585000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    312627000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1390241555                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18784.729586                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15784.729586                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1390221752                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       371994000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    312585000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    312627000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            19803                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.679847                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1392.325794                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.679846                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1392.325384                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1390241555                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18784.729586                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1390221752                       # number of overall hits
-system.cpu.icache.overall_miss_latency      371994000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                19803                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    312585000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    312627000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           19803                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  18364                       # number of replacements
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1392.325794                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1392.325384                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1390221752                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses           72780                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                   1                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   3784508000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999986                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses             72779                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2911160000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999986                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses        72779                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                6687                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   3436836000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.908120                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses             66093                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           1480964                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 41422                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   74856184000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.972030                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1439542                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  57581680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.972030                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1439542                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           1496                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency     77792000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             1496                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency     59840000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         1496                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           74582                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               74582                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                 67385                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   73506108000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.954499                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1413579                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56543160000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954499                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1413579                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          107259                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.032374                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.050081                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            1553744                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  41423                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency    78640692000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.973340                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1512321                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  74072                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    76942944000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.952327                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1479672                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency  60492840000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.973340                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1512321                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  59186880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.952327                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1479672                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.927467                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.046803                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         30391.242944                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          1533.635543                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.881760                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.092816                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         28893.501877                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3041.393075                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           1553744                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 41423                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency   78640692000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.973340                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1512321                       # number of overall misses
+system.cpu.l2cache.overall_hits                 74072                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   76942944000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.952327                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1479672                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency  60492840000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.973340                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1512321                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  59186880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.952327                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1479672                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               1472894                       # number of replacements
-system.cpu.l2cache.sampled_refs               1505603                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               1478797                       # number of replacements
+system.cpu.l2cache.sampled_refs               1511517                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             31924.878487                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   48742                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             31934.894953                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   75699                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66101                       # number of writebacks
+system.cpu.l2cache.writebacks                   66099                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4742699432                       # number of cpu cycles simulated
+system.cpu.numCycles                       4739792356                       # number of cpu cycles simulated
 system.cpu.num_insts                       1832675505                       # Number of instructions executed
 system.cpu.num_refs                         908401146                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1411                       # Number of system calls
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index b77e3983a..5fb4a0cfa 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -191,7 +191,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
index aa460e79e..c3421945c 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:06
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:19:32
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 104900991500 because target called exit()
+Exiting @ tick 104166942500 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 0547798c7..81763d717 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  31368                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 223704                       # Number of bytes of host memory used
-host_seconds                                  2816.26                       # Real time elapsed on the host
-host_tick_rate                               37248320                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  58405                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209896                       # Number of bytes of host memory used
+host_seconds                                  1512.56                       # Real time elapsed on the host
+host_tick_rate                               68868083                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
-sim_seconds                                  0.104901                       # Number of seconds simulated
-sim_ticks                                104900991500                       # Number of ticks simulated
+sim_seconds                                  0.104167                       # Number of seconds simulated
+sim_ticks                                104166942500                       # Number of ticks simulated
 system.cpu.AGEN-Unit.agens                   35224018                       # Number of Address Generations
 system.cpu.Branch-Predictor.BTBHitPct       41.015608                       # BTB Hit Percentage
 system.cpu.Branch-Predictor.BTBHits           4719981                       # Number of BTB hits
@@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect       434959
 system.cpu.Execution-Unit.predictedTakenIncorrect       217237                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.Mult-Div-Unit.multiplies             41101                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses    156429013                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads     103882132                       # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses    156429280                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads     103882399                       # Number of Reads from Register File
 system.cpu.RegFile-Manager.regFileWrites     52546881                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards        2136233                       # Number of Registers Read Through Forwarding Logic
-system.cpu.activity                         84.755939                       # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards        2135966                       # Number of Registers Read Through Forwarding Logic
+system.cpu.activity                         85.354290                       # Percentage of cycles cpu is active
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
 system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
 system.cpu.comInts                           30457224                       # Number of Integer instructions committed
@@ -42,28 +42,28 @@ system.cpu.comStores                         14844619                       # Nu
 system.cpu.committedInsts                    88340673                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions Simulated (Total)
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.cpi                               2.374919                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         2.374919                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.358301                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         2.358301                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 37505.438897                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34394.916565                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2312217500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     2279055500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2123402000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2090041500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              14466192                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    8303642500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010072                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              147185                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   7862076500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010072                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         147185                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 52898.208639                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49865.139506                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              14469799                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    7595019000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.009825                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              143578                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   7159537000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         143578                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
@@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51049.814620                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                34682064                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     10615860000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005960                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                207951                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 48320.843773                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 45264.742297                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                34685671                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9874074500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.005857                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                204344                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   9985478500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005960                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           207951                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   9249578500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           204344                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995330                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4076.871208                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995297                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.738170                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51049.814620                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 48320.843773                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 45264.742297                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               34682064                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    10615860000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005960                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               207951                       # number of overall misses
+system.cpu.dcache.overall_hits               34685671                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9874074500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.005857                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               204344                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   9985478500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005960                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          207951                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   9249578500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          204344                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 200248                       # number of replacements
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4076.871208                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.738170                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              834930000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   149164                       # number of writebacks
+system.cpu.dcache.warmup_cycle              834588000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   161221                       # number of writebacks
 system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                     34890015                       # DTB hits
@@ -126,50 +126,50 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           97023272                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19062.290643                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               96943862                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     1513736500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_avg_miss_latency 19054.387931                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15836.123818                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               96943861                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency     1513128000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000818                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                79410                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              1586                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency   1233073000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                79411                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              1587                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency   1232430500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000802                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           77824                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          800                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                1245.680793                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                1245.680780                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets         4000                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            97023272                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19062.290643                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                96943862                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      1513736500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_avg_miss_latency 19054.387931                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15836.123818                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                96943861                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency      1513128000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000818                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 79410                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               1586                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   1233073000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                 79411                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               1587                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency   1232430500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000802                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            77824                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.914717                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1873.340733                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.914428                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1872.748134                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           97023272                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19062.290643                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 19054.387931                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15836.123818                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               96943862                       # number of overall hits
-system.cpu.icache.overall_miss_latency     1513736500                       # number of overall miss cycles
+system.cpu.icache.overall_hits               96943861                       # number of overall hits
+system.cpu.icache.overall_miss_latency     1513128000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000818                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                79410                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              1586                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   1233073000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                79411                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              1587                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency   1232430500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000802                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           77824                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  75778                       # number of replacements
 system.cpu.icache.sampled_refs                  77824                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1873.340733                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 96943862                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1872.748134                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 96943861                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        31982342                       # Number of cycles cpu's stages were not processed
-system.cpu.ipc                               0.421067                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.421067                       # IPC: Total IPC of All Threads
+system.cpu.idleCycles                        30511976                       # Number of cycles cpu's stages were not processed
+system.cpu.ipc                               0.424034                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.424034                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -201,105 +201,96 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                  54                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   7525926000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999624                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            143524                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   5740992500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999624                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       143524                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52440.979168                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.144510                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits               12099                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   6894887500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.915732                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            131479                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   5259179000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915732                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       131479                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            138590                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 95311                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    2263590000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.312281                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               43279                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1731370500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.312281                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          43279                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           3607                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    186907000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             3607                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    144288500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         3607                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          149164                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              149164                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_avg_miss_latency 52303.399887                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.932662                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 96118                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    2221430000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.306458                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               42472                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1699089500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.306458                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          42472                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          161221                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              161221                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.646134                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.718111                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses             282168                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52405.560939                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  95365                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9789516000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.662028                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               186803                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 52407.387713                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.313588                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 108217                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     9116317500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.616480                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               173951                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7472363000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.662028                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          186803                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   6958268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.616480                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          173951                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.089575                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.471967                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2935.193659                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15465.399858                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.086814                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.481065                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2844.720641                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15763.536508                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            282168                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52405.560939                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52407.387713                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.313588                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 95365                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9789516000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.662028                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              186803                       # number of overall misses
+system.cpu.l2cache.overall_hits                108217                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    9116317500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.616480                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              173951                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7472363000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.662028                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         186803                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   6958268500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.616480                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         173951                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                147725                       # number of replacements
-system.cpu.l2cache.sampled_refs                173054                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                147575                       # number of replacements
+system.cpu.l2cache.sampled_refs                172919                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18400.593517                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  111816                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18608.257148                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  124175                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  120606                       # number of writebacks
-system.cpu.numCycles                        209801984                       # number of cpu cycles simulated
-system.cpu.runCycles                        177819642                       # Number of cycles cpu stages are processed.
+system.cpu.l2cache.writebacks                  120508                       # number of writebacks
+system.cpu.numCycles                        208333886                       # number of cpu cycles simulated
+system.cpu.runCycles                        177821910                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles               112774700                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles               111306602                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-0.runCycles                 97027284                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              46.247076                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles               121437923                       # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles                 88364061                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              42.117839                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles               119986198                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization              46.572973                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles               119969888                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles                 88363998                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization              42.414607                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles               118518100                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-2.runCycles                 89815786                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              42.809789                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles               174570714                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization              43.111463                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles               173102616                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-3.runCycles                 35231270                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              16.792630                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles               121461311                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization              16.910965                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles               119993213                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-4.runCycles                 88340673                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              42.106691                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles                     209801984                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization              42.403411                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles                     208333886                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 0c3775172..4fc48d6be 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
index 90ad95ec6..5eaa6d66d 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:53:46
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:41:46
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 27109454000 because target called exit()
+Exiting @ tick 27033689000 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index aa0ed940f..e70c0ce38 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,340 +1,340 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 111480                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216720                       # Number of bytes of host memory used
-host_seconds                                   713.95                       # Real time elapsed on the host
-host_tick_rate                               37970836                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 221900                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202972                       # Number of bytes of host memory used
+host_seconds                                   358.68                       # Real time elapsed on the host
+host_tick_rate                               75369122                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    79591756                       # Number of instructions simulated
-sim_seconds                                  0.027109                       # Number of seconds simulated
-sim_ticks                                 27109454000                       # Number of ticks simulated
+sim_seconds                                  0.027034                       # Number of seconds simulated
+sim_ticks                                 27033689000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  8023938                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              14145639                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               34256                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             455419                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           10571328                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 16274912                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1940184                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits                  8073345                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              14152511                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               36189                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             458905                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           10574319                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 16281513                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1942543                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               13754477                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           3318027                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events           3315405                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     51708884                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.708423                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.329205                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     51596234                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.712153                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.330354                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     22519798     43.55%     43.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     11308699     21.87%     65.42% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      5100268      9.86%     75.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      3555628      6.88%     82.16% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2564108      4.96%     87.12% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1506181      2.91%     90.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6      1020225      1.97%     92.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       815950      1.58%     93.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      3318027      6.42%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     22410479     43.43%     43.43% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     11292136     21.89%     65.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      5122096      9.93%     75.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      3547417      6.88%     82.12% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2566622      4.97%     87.10% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      1508057      2.92%     90.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6      1006074      1.95%     91.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       827948      1.60%     93.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      3315405      6.43%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     51708884                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total     51596234                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  88340672                       # Number of instructions committed
 system.cpu.commit.COM:loads                  20379399                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   35224018                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts            360224                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts            362306                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts         8384811                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         8339248                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.681213                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.681213                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses           43                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits               43                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           20456575                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               20307098                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4527091000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.007307                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses               149477                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits             87887                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency   1284503500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.003011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses           61590                       # number of ReadReq MSHR misses
+system.cpu.cpi                               0.679309                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.679309                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses           44                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits               44                       # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses           20462752                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               20316340                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     4411629000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.007155                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses               146412                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits             84834                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency   1258305500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses           61578                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              13566176                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   33748584999                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.071660                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1047201                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits           900041                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   5258205499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010070                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         147160                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              13581378                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   31995900999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.070620                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1031999                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits           888502                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   4723892999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009820                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         143497                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        27000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 165.209324                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                 165.294463                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        27000                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            35069952                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31984.941646                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                33873274                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     38275675999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.034123                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1196678                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits             987928                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   6542708999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005952                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           208750                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            35076129                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30895.443100                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                33897718                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     36407529999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.033596                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1178411                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits             973336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   5982198499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.005847                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           205075                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995492                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4077.536069                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           35069952                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31984.941646                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.995480                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4077.485052                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           35076129                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30895.443100                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               33873274                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    38275675999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.034123                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1196678                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits            987928                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   6542708999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005952                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          208750                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits               33897718                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    36407529999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.033596                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1178411                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits            973336                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   5982198499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.005847                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          205075                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                 200988                       # number of replacements
-system.cpu.dcache.sampled_refs                 205084                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                 200979                       # number of replacements
+system.cpu.dcache.sampled_refs                 205075                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4077.536069                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 33881789                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              181403000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   149251                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        3489554                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          96109                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       3659886                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       101890177                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          28536030                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           19538571                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1305079                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         281240                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         144729                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                 36643462                       # DTB accesses
-system.cpu.dtb.data_acv                            34                       # DTB access violations
-system.cpu.dtb.data_hits                     36467174                       # DTB hits
-system.cpu.dtb.data_misses                     176288                       # DTB misses
+system.cpu.dcache.tagsinuse               4077.485052                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 33897762                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              181365000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   161485                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles        3372983                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          97431                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       3660168                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       101877731                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          28530714                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           19554245                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         1300005                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         281200                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles         138292                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                 36642762                       # DTB accesses
+system.cpu.dtb.data_acv                            38                       # DTB access violations
+system.cpu.dtb.data_hits                     36466941                       # DTB hits
+system.cpu.dtb.data_misses                     175821                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 21569273                       # DTB read accesses
-system.cpu.dtb.read_acv                            32                       # DTB read access violations
-system.cpu.dtb.read_hits                     21411172                       # DTB read hits
-system.cpu.dtb.read_misses                     158101                       # DTB read misses
-system.cpu.dtb.write_accesses                15074189                       # DTB write accesses
+system.cpu.dtb.read_accesses                 21568925                       # DTB read accesses
+system.cpu.dtb.read_acv                            36                       # DTB read access violations
+system.cpu.dtb.read_hits                     21411469                       # DTB read hits
+system.cpu.dtb.read_misses                     157456                       # DTB read misses
+system.cpu.dtb.write_accesses                15073837                       # DTB write accesses
 system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_hits                    15056002                       # DTB write hits
-system.cpu.dtb.write_misses                     18187                       # DTB write misses
-system.cpu.fetch.Branches                    16274912                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  13386326                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      33268098                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                152194                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      103463438                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                  573170                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.300170                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           13386326                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches            9964122                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.908254                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           53013963                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.951626                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.945013                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits                    15055472                       # DTB write hits
+system.cpu.dtb.write_misses                     18365                       # DTB write misses
+system.cpu.fetch.Branches                    16281513                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  13394440                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      33285984                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                153835                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      103456008                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                  576870                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.301134                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           13394440                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           10015888                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.913464                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           52896239                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.955829                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.944816                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 33159204     62.55%     62.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1896528      3.58%     66.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1503537      2.84%     68.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1853022      3.50%     72.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3942692      7.44%     79.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1853723      3.50%     83.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   688430      1.30%     84.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1103809      2.08%     86.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7013018     13.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 33031612     62.45%     62.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1863332      3.52%     65.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1548849      2.93%     68.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1858475      3.51%     72.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3937136      7.44%     79.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1852242      3.50%     83.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   690247      1.30%     84.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1146451      2.17%     86.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6967895     13.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             53013963                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses           13386326                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  9552.485505                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  6054.988859                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               13297330                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      850133000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.006648                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                88996                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              2824                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    521770500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.006437                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           86172                       # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total             52896239                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses           13394440                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  9549.980865                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  6051.228388                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               13305596                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      848458500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.006633                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                88844                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              2837                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    520448000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.006421                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           86007                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                 154.313284                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                 154.705439                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            13386326                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  9552.485505                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  6054.988859                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                13297330                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       850133000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.006648                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 88996                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               2824                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    521770500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.006437                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            86172                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses            13394440                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  9549.980865                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  6051.228388                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                13305596                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       848458500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.006633                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 88844                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               2837                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    520448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.006421                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            86007                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.936859                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1918.688120                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           13386326                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  9552.485505                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  6054.988859                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.936980                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1918.935161                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           13394440                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  9549.980865                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  6051.228388                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               13297330                       # number of overall hits
-system.cpu.icache.overall_miss_latency      850133000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.006648                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                88996                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              2824                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    521770500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.006437                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           86172                       # number of overall MSHR misses
+system.cpu.icache.overall_hits               13305596                       # number of overall hits
+system.cpu.icache.overall_miss_latency      848458500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.006633                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                88844                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              2837                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    520448000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.006421                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           86007                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                  84124                       # number of replacements
-system.cpu.icache.sampled_refs                  86171                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                  83959                       # number of replacements
+system.cpu.icache.sampled_refs                  86006                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1918.688120                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 13297330                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1918.935161                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 13305596                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1204946                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 14764091                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       9400465                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.566510                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     36986360                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                   15307304                       # Number of stores executed
+system.cpu.idleCycles                         1171140                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 14765953                       # Number of branches executed
+system.cpu.iew.EXEC:nop                       9399098                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.570651                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     36985556                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                   15306955                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  42224308                       # num instructions consuming a value
-system.cpu.iew.WB:count                      84456261                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.765793                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  42195611                       # num instructions consuming a value
+system.cpu.iew.WB:count                      84441959                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.765718                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  32335073                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.557690                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       84693859                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts               401805                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                  605778                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              23014883                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts               5009                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            349401                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             16347988                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts            99082046                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              21679056                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            539226                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              84934458                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  11054                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  32309953                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.561791                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       84679067                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               403539                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  558736                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              23014663                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts               5005                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            344896                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             16344120                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            99062445                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              21678601                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            539249                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              84921008                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                   9867                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                  8978                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                1305079                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                 42917                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                  8786                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                1300005                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                 41358                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked           15                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          953186                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses          709                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked           22                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          947297                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses          703                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        20710                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         1355                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      2635484                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      1503369                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          20710                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       131758                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         270047                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.467970                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.467970                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation        20504                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads         1356                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      2635264                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      1499501                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          20504                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       133144                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         270395                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.472085                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.472085                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        47968991     56.12%     56.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          42906      0.05%     56.17% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        47958643     56.12%     56.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          42972      0.05%     56.17% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     56.17% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd        122147      0.14%     56.31% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd        122098      0.14%     56.31% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCmp            86      0.00%     56.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt        122353      0.14%     56.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult           51      0.00%     56.46% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv         38520      0.05%     56.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt        122222      0.14%     56.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult           51      0.00%     56.45% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv         38519      0.05%     56.50% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     56.50% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       21790369     25.49%     82.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite      15388261     18.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       21787306     25.49%     81.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite      15388360     18.01%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         85473684                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                995540                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.011647                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total         85460257                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                970619                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.011358                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            102737     10.32%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     10.32% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           453943     45.60%     55.92% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          438860     44.08%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             98326     10.13%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     10.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead           436344     44.96%     55.09% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          435949     44.91%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     53013963                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.612286                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.719350                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     52896239                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.615621                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.720411                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      17564950     33.13%     33.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      14012876     26.43%     59.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       8103290     15.29%     74.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       4796735      9.05%     83.90% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       4597424      8.67%     92.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2085134      3.93%     96.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1155738      2.18%     98.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        468299      0.88%     99.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8        229517      0.43%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      17480622     33.05%     33.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      13990970     26.45%     59.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2       8059116     15.24%     74.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       4840128      9.15%     83.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       4581404      8.66%     92.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       2086569      3.94%     96.49% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       1156021      2.19%     98.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        475188      0.90%     99.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8        226221      0.43%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     53013963                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.576455                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                   89676572                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  85473684                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                5009                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined         9869392                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             46778                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved            426                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined      6797277                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     52896239                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.580625                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                   89658342                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  85460257                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                5005                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined         9847468                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             48230                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved            422                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined      6786581                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                13413339                       # ITB accesses
+system.cpu.itb.fetch_accesses                13421357                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    13386326                       # ITB hits
-system.cpu.itb.fetch_misses                     27013                       # ITB misses
+system.cpu.itb.fetch_hits                    13394440                       # ITB hits
+system.cpu.itb.fetch_misses                     26917                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -343,107 +343,98 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_acv                            0                       # DTB write access violations
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses          143495                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                  61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   4924813000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999575                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            143434                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4479705500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999575                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       143434                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses            147761                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                103271                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1518815500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.301094                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               44490                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1380712500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.301094                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          44490                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           3671                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    124700500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             3671                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    113902500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         3671                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          149251                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              149251                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_accesses          143498                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits               12072                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   4509238000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.915873                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            131426                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4101673500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915873                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       131426                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses            147584                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                103938                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1489830500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.295737                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               43646                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1354463000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.295737                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          43646                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          161485                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              161485                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.688286                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.759972                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses             291256                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34288.480982                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 103332                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     6443628500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.645219                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               187924                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses             291082                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34266.293296                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 116010                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     5999068500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.601453                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               175072                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   5860418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.645219                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          187924                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   5456136500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.601453                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          175072                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.096999                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.471977                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          3178.468873                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15465.728229                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses            291256                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34288.480982                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.094631                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.481096                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3100.873906                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15764.562961                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses            291082                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34266.293296                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                103332                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    6443628500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.645219                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              187924                       # number of overall misses
+system.cpu.l2cache.overall_hits                116010                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    5999068500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.601453                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              175072                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   5860418000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.645219                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         187924                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   5456136500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.601453                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         175072                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                148884                       # number of replacements
-system.cpu.l2cache.sampled_refs                174227                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                148714                       # number of replacements
+system.cpu.l2cache.sampled_refs                174071                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18644.197102                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  119918                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18865.436867                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  132289                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  120621                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          12607383                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11255649                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             23014883                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16347988                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                         54218909                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles          2001211                       # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks                  120514                       # number of writebacks
+system.cpu.memDep0.conflictingLoads          12522416                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11202183                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             23014663                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16344120                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                         54067379                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles          1899423                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       52546881                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents           58273                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          28932787                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1273359                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents             32                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups      121782078                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       101070010                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     60804975                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           19289152                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1305079                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        1405067                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           8258094                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles        80667                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts         5283                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            2766751                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts         5281                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                           41950                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents           50756                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          28921656                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        1270692                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents             25                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups      121761220                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       101056260                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     60792051                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           19304913                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         1300005                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        1392613                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps           8245170                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles        77629                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts         5282                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts            2690297                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts         5280                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                           40629                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 1aa6cf383..6c6429621 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
index a83443919..6bbe0f2d0 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:57:42
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:47:45
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 135015129000 because target called exit()
+Exiting @ tick 134276988000 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index e11ad72a2..ba780f9a8 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1159310                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215356                       # Number of bytes of host memory used
-host_seconds                                    76.20                       # Real time elapsed on the host
-host_tick_rate                             1771821789                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1350777                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201544                       # Number of bytes of host memory used
+host_seconds                                    65.40                       # Real time elapsed on the host
+host_tick_rate                             2053162286                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    88340673                       # Number of instructions simulated
-sim_seconds                                  0.135015                       # Number of seconds simulated
-sim_ticks                                135015129000                       # Number of ticks simulated
+sim_seconds                                  0.134277                       # Number of seconds simulated
+sim_ticks                                134276988000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     2294180000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     2261000000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2111882000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2078702000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              14466192                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    8240064000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.010072                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              147185                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   7798509000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010072                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         147185                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              14469799                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    7532210000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.009825                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              143578                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   7101476000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         143578                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50657.337546                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47657.337546                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                34682064                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     10534244000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005960                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                207951                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 47925.116470                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                34685671                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      9793210000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.005857                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                204344                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   9910391000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005960                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           207951                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   9180178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           204344                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995838                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4078.950714                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995815                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4078.858373                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50657.337546                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47657.337546                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 47925.116470                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               34682064                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    10534244000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005960                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               207951                       # number of overall misses
+system.cpu.dcache.overall_hits               34685671                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     9793210000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.005857                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               204344                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   9910391000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005960                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          207951                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   9180178000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          204344                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 200248                       # number of replacements
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4078.950714                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4078.858373                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              943578000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   149164                       # number of writebacks
+system.cpu.dcache.warmup_cycle              943232000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   161222                       # number of writebacks
 system.cpu.dtb.data_accesses                 34987415                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                     34890015                       # DTB hits
@@ -90,13 +90,13 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                    14613377                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           88438074                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18802.449108                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15802.449108                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 18793.107960                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               88361638                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     1437184000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency     1436470000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000864                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                76436                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency   1207876000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   1207162000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000864                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           76436                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -108,31 +108,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            88438074                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18802.449108                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15802.449108                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 18793.107960                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                88361638                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      1437184000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency      1436470000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000864                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 76436                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   1207876000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   1207162000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000864                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            76436                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.913991                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1871.853872                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.913772                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1871.404551                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18802.449108                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15802.449108                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 18793.107960                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               88361638                       # number of overall hits
-system.cpu.icache.overall_miss_latency     1437184000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency     1436470000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000864                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                76436                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   1207876000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   1207162000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000864                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           76436                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  74391                       # number of replacements
 system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1871.853872                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1871.404551                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 88361638                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,37 +164,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                  54                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   7463248000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999624                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            143524                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   5740960000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999624                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       143524                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits               12099                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   6836908000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.915732                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            131479                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   5259160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915732                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       131479                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            137202                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 94094                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    2241616000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.314194                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               43108                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1724320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.314194                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          43108                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           3607                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51596.340449                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    186108000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             3607                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    144280000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         3607                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          149164                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              149164                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                 94901                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    2199652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.308312                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               42301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1692040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.308312                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          42301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          161222                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              161222                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.639727                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.711777                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             280780                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  94148                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9704864000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.664691                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               186632                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 107000                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     9036560000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.618919                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               173780                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   7465280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.664691                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          186632                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   6951200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.618919                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          173780                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.088307                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.473299                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2893.659899                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15509.045444                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.085649                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.482430                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2806.549776                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15808.263557                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 94148                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9704864000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.664691                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              186632                       # number of overall misses
+system.cpu.l2cache.overall_hits                107000                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    9036560000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.618919                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              173780                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   7465280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.664691                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         186632                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   6951200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.618919                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         173780                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                147555                       # number of replacements
-system.cpu.l2cache.sampled_refs                172883                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                147405                       # number of replacements
+system.cpu.l2cache.sampled_refs                172748                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             18402.705343                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  110598                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18614.813333                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  122958                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                  120604                       # number of writebacks
+system.cpu.l2cache.writebacks                  120506                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        270030258                       # number of cpu cycles simulated
+system.cpu.numCycles                        268553976                       # number of cpu cycles simulated
 system.cpu.num_insts                         88340673                       # Number of instructions executed
 system.cpu.num_refs                          35321418                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            4583                       # Number of system calls
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
index 2a754cafb..631dd37fd 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
index 92e232392..935e56759 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:53:04
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:54
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 133464153000 because target called exit()
+Exiting @ tick 133078695000 because target called exit()
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 0ce9c5c87..eb164565e 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1245224                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 218772                       # Number of bytes of host memory used
-host_seconds                                    78.70                       # Real time elapsed on the host
-host_tick_rate                             1695886374                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1323688                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204612                       # Number of bytes of host memory used
+host_seconds                                    74.03                       # Real time elapsed on the host
+host_tick_rate                             1797531911                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    97997303                       # Number of instructions simulated
-sim_seconds                                  0.133464                       # Number of seconds simulated
-sim_ticks                                133464153000                       # Number of ticks simulated
+sim_seconds                                  0.133079                       # Number of seconds simulated
+sim_ticks                                133078695000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           27164439                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35865.411818                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32865.411818                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 35146.149639                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32146.149639                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               27111418                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     1901620000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     1863484000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                53021                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1742557000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1704421000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           53021                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          19865820                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55969.020638                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52969.020638                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              19755779                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    6158887000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.005539                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              110041                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5828764000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005539                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         110041                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54270.699030                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51270.699030                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              19758786                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5808810000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005388                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              107034                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5487708000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005388                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         107034                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 292.838112                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            47030259                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 49432.160773                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 46432.160773                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                46867197                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      8060507000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.003467                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                163062                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 47935.359720                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 44935.359720                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                46870204                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      7672294000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.003403                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                160055                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   7571321000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.003467                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           163062                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   7192129000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.003403                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           160055                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.995361                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4076.997954                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995347                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4076.942972                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           47030259                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 49432.160773                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 46432.160773                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 47935.359720                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 44935.359720                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               46867197                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     8060507000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.003467                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               163062                       # number of overall misses
+system.cpu.dcache.overall_hits               46870204                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     7672294000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.003403                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               160055                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   7571321000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.003467                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          163062                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   7192129000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.003403                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          160055                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 155959                       # number of replacements
 system.cpu.dcache.sampled_refs                 160055                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4076.997954                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.942972                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 46870204                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1079446000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   110614                       # number of writebacks
+system.cpu.dcache.warmup_cycle             1079223000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   122819                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -83,13 +83,13 @@ system.cpu.dtb.write_accesses                       0                       # DT
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
 system.cpu.icache.ReadReq_accesses           78097320                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24224.561032                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21224.561032                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits               78078412                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      458038000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency    401314000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -101,31 +101,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses            78097320                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24224.561032                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21224.561032                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                78078412                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       458038000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    401314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    401062000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.847896                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1736.491216                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.847769                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1736.230096                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           78097320                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24224.561032                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21224.561032                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits               78078412                       # number of overall hits
-system.cpu.icache.overall_miss_latency      458038000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                18908                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    401314000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                  16890                       # number of replacements
 system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1736.491216                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1736.230096                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 78078412                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses          107034                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                  81                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   5561556000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999243                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            106953                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4278120000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999243                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       106953                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                4407                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.958826                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958826                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses             71929                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 39723                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    1674712000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.447747                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               32206                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1288240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.447747                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          32206                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           3007                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51878.949119                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    156000000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             3007                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    120280000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         3007                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          110614                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              110614                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                 40637                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    1627184000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.435040                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               31292                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1251680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435040                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          31292                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          122819                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              122819                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.368048                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.466930                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             178963                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  39804                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     7236268000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.777585                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               139159                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                  45044                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     6963788000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.748306                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               133919                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   5566360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.777585                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          139159                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   5356760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.748306                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          133919                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.070819                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.476669                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2320.602092                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15619.501011                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.066136                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.489058                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2167.134157                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16025.466133                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            178963                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 39804                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    7236268000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.777585                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              139159                       # number of overall misses
+system.cpu.l2cache.overall_hits                 45044                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    6963788000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.748306                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              133919                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   5566360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.777585                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         139159                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   5356760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.748306                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         133919                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                114078                       # number of replacements
-system.cpu.l2cache.sampled_refs                132866                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                113661                       # number of replacements
+system.cpu.l2cache.sampled_refs                132491                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             17940.103104                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   48901                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18192.600290                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   61864                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   88549                       # number of writebacks
+system.cpu.l2cache.writebacks                   88450                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        266928306                       # number of cpu cycles simulated
+system.cpu.numCycles                        266157390                       # number of cpu cycles simulated
 system.cpu.num_insts                         97997303                       # Number of instructions executed
 system.cpu.num_refs                          47871034                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
index c85b36dc7..08b8aa7ee 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
index b0fb854c0..e214aaa33 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:03:41
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:06:02
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 16:35:02
+M5 executing on phenom
 command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 203281649000 because target called exit()
+Exiting @ tick 202941992000 because target called exit()
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index ca8b32bef..d33aa6f85 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,43 +1,43 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1039608                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 220432                       # Number of bytes of host memory used
-host_seconds                                   130.95                       # Real time elapsed on the host
-host_tick_rate                             1552328099                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1222037                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 206136                       # Number of bytes of host memory used
+host_seconds                                   111.40                       # Real time elapsed on the host
+host_tick_rate                             1821674437                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   136139203                       # Number of instructions simulated
-sim_seconds                                  0.203282                       # Number of seconds simulated
-sim_ticks                                203281649000                       # Number of ticks simulated
+sim_seconds                                  0.202942                       # Number of seconds simulated
+sim_ticks                                202941992000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38539.616255                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35539.616255                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               37185802                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     1753514000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     1709246000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                45499                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1617017000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1572749000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses           45499                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits                  15879                       # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency        2072000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate          0.002325                       # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses                   37                       # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency      1961000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.002325                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses              37                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency        30800                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency        27800                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency         462000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency       417000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55967.131927                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52967.131927                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              20756479                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    6034656000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.005168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              107825                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5711181000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005168                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         107825                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              20759140                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5738404000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005040                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              105164                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5422912000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         105164                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
@@ -47,50 +47,50 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50795.504944                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47795.504944                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                57942281                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      7788170000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002639                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                153324                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 49432.508313                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      7447650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   7328198000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002639                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses           153324                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency   6995661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997956                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4087.629454                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.997953                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50795.504944                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47795.504944                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               57942281                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     7788170000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002639                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses               153324                       # number of overall misses
+system.cpu.dcache.overall_hits               57944942                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     7447650000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               150663                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   7328198000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002639                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses          153324                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency   6995661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                 146582                       # number of replacements
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4087.629454                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4087.617150                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              776960000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   108328                       # number of writebacks
+system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   118818                       # number of writebacks
 system.cpu.icache.ReadReq_accesses          134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 16931.987339                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13931.987339                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16930.864488                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits              134366560                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency     3166688000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency     3166478000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.001390                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency   2605616000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   2605406000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -102,31 +102,31 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           134553584                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 16931.987339                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13931.987339                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 16930.864488                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
 system.cpu.icache.demand_hits               134366560                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency      3166688000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency      3166478000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.001390                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency   2605616000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   2605406000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.978873                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           2004.731937                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.978868                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 16931.987339                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13931.987339                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits              134366560                       # number of overall hits
-system.cpu.icache.overall_miss_latency     3166688000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency     3166478000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.001390                       # miss rate for overall accesses
 system.cpu.icache.overall_misses               187024                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency   2605616000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   2605406000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.001390                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -134,45 +134,36 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                 184976                       # number of replacements
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               2004.731937                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               2004.721102                       # Cycle average of tags in use
 system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle           144738462000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.warmup_cycle           144544557000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.l2cache.ReadExReq_accesses          105179                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits                  84                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency   5464940000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.999201                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses            105095                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4203800000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.999201                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses       105095                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                3599                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency   5282160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.965782                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            101580                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4063200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.965782                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       101580                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses            232523                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                192883                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    2061280000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.170478                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses               39640                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1585600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.170478                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses          39640                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses           2683                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51689.899366                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency    138684000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses             2683                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    107320000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses         2683                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses          108328                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits              108328                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits                193942                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    2006212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.165923                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               38581                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1543240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165923                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          38581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          118818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              118818                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.441131                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.525179                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             337702                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                 192967                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     7526220000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.428588                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               144735                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 197541                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     7288372000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.415043                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               140161                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   5789400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.428588                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          144735                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   5606440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.415043                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          140161                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.127128                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.467489                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          4165.731733                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15318.691405                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.121030                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.481204                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                192967                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    7526220000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.428588                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              144735                       # number of overall misses
+system.cpu.l2cache.overall_hits                197541                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    7288372000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.415043                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              140161                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   5789400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.428588                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         144735                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   5606440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.415043                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         140161                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements                120481                       # number of replacements
-system.cpu.l2cache.sampled_refs                139283                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                120138                       # number of replacements
+system.cpu.l2cache.sampled_refs                139002                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             19484.423138                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  200725                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             19734.031622                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  212003                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   87388                       # number of writebacks
+system.cpu.l2cache.writebacks                   87265                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        406563298                       # number of cpu cycles simulated
+system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
 system.cpu.num_insts                        136139203                       # Number of instructions executed
 system.cpu.num_refs                          58160249                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index a93c146ce..52a80c785 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 13489d0ab..edfeea16a 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:05:40
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:52
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +28,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 732922365000 because target called exit()
+Exiting @ tick 725600064000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 3840a0336..c65dff4b5 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,54 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 115207                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207548                       # Number of bytes of host memory used
-host_seconds                                 15068.91                       # Real time elapsed on the host
-host_tick_rate                               48638035                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 201279                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193732                       # Number of bytes of host memory used
+host_seconds                                  8625.07                       # Real time elapsed on the host
+host_tick_rate                               84126874                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1736043781                       # Number of instructions simulated
-sim_seconds                                  0.732922                       # Number of seconds simulated
-sim_ticks                                732922365000                       # Number of ticks simulated
+sim_seconds                                  0.725600                       # Number of seconds simulated
+sim_ticks                                725600064000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                297651815                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups             304473054                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect                 146                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect           19905340                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted          266187209                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                345286425                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                 23890708                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits                297121632                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups             303782824                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                 142                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect           19928405                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted          265297852                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                344822488                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                 23968882                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches              214632552                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events          63402454                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events          61479856                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples   1362326064                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.335789                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     2.108307                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples   1350419468                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.347567                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     2.103580                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0    722221726     53.01%     53.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1    260663635     19.13%     72.15% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2    126275090      9.27%     81.42% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3     73614843      5.40%     86.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4     49214339      3.61%     90.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5     31342415      2.30%     92.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6     24208215      1.78%     94.51% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7     11383347      0.84%     95.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8     63402454      4.65%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0    709166800     52.51%     52.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1    257980850     19.10%     71.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2    128756395      9.53%     81.15% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3     75319653      5.58%     86.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4     50577217      3.75%     90.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5     29303662      2.17%     92.65% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6     27183744      2.01%     94.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7     10651291      0.79%     95.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8     61479856      4.55%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total   1362326064                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total   1350419468                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                1819780126                       # Number of instructions committed
 system.cpu.commit.COM:loads                 445666361                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                  606571343                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts          19904825                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts          19927893                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts       616386841                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       598409142                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                               0.844359                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.844359                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.835924                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.835924                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        38500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35500                       # average LoadLockedReq mshr miss latency
@@ -59,292 +59,290 @@ system.cpu.dcache.LoadLockedReq_misses              1                       # nu
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses          521630579                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 16446.832647                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11014.947389                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              511650921                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   164133765000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.019132                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              9979658                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits           2703270                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  80149031000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.013949                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         7276388                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses          522152433                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 16274.867726                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10956.764593                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              512203202                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency   161922418500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.019054                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              9949231                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits           2672880                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  79725265000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.013935                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         7276351                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32545.971387                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34322.334946                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             155766779                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  161484094789                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.030870                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             4961723                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          2963011                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency  68600462724                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.012435                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1998712                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5974.555782                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 30410.724976                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  72.882698                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs            121015                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65147                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs    723010868                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   1981167500                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 26917.452067                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20483.226007                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             155989745                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency  127555264405                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.029483                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             4738757                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          2853938                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency  38607173559                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011727                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1884819                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3154.492044                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  72.937504                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs             37706                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65110                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs    118943277                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   1980503500                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           682359081                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 21793.023000                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16037.508353                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               667417700                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    325617859789                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.021897                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses              14941381                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            5666281                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 148749493724                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.013593                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9275100                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses           682880935                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 19708.464012                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12916.738644                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               668192947                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    289477682905                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.021509                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses              14687988                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            5526818                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 118332438559                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.013415                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9161170                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997469                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_%::1                  -0.002947                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4085.632664                       # Average occupied blocks per context
-system.cpu.dcache.occ_blocks::1            -12.069593                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses          682359081                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 21793.023000                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16037.508353                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.997445                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4085.532750                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses          682880935                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 19708.464012                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12916.738644                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              667417700                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   325617859789                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.021897                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses             14941381                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           5666281                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 148749493724                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.013593                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9275100                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits              668192947                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   289477682905                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.021509                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses             14687988                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           5526818                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 118332438559                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.013415                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9161170                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                9156983                       # number of replacements
-system.cpu.dcache.sampled_refs                9161079                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                9157075                       # number of replacements
+system.cpu.dcache.sampled_refs                9161171                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4079.597867                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                667684156                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             7084801000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2367711                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       93349702                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred            598                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved      54504022                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts      2803113220                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles         722066213                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles          542175542                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles        91814713                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts           1721                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        4734607                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                769403639                       # DTB accesses
+system.cpu.dcache.tagsinuse               4085.532750                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                668192949                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             7084076000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3077872                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       79445863                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred            739                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved      54863160                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts      2804005174                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles         723465377                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles          543368654                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles        89450574                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts           1719                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        4139574                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                765936230                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    753449541                       # DTB hits
-system.cpu.dtb.data_misses                   15954098                       # DTB misses
+system.cpu.dtb.data_hits                    750636298                       # DTB hits
+system.cpu.dtb.data_misses                   15299932                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                567301584                       # DTB read accesses
+system.cpu.dtb.read_accesses                565223455                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    558063709                       # DTB read hits
-system.cpu.dtb.read_misses                    9237875                       # DTB read misses
-system.cpu.dtb.write_accesses               202102055                       # DTB write accesses
+system.cpu.dtb.read_hits                    556102001                       # DTB read hits
+system.cpu.dtb.read_misses                    9121454                       # DTB read misses
+system.cpu.dtb.write_accesses               200712775                       # DTB write accesses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                   195385832                       # DTB write hits
-system.cpu.dtb.write_misses                   6716223                       # DTB write misses
-system.cpu.fetch.Branches                   345286425                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                 353801341                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                     911477048                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes               8513687                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                     2856997588                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                28043242                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.235555                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles          353801341                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches          321542523                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        1.949045                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples         1454140777                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.964732                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.867668                       # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits                   194534297                       # DTB write hits
+system.cpu.dtb.write_misses                   6178478                       # DTB write misses
+system.cpu.fetch.Branches                   344822488                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                 355034186                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                     913253672                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes               8462729                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                     2857790040                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                28218175                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.237612                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles          355034186                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches          321090514                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        1.969260                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples         1439870042                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.984756                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.874458                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                896465106     61.65%     61.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 48268270      3.32%     64.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30594278      2.10%     67.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 50900501      3.50%     70.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                123419810      8.49%     79.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 68033881      4.68%     83.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 46960603      3.23%     86.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 36759628      2.53%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                152738700     10.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                881650589     61.23%     61.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 48391639      3.36%     64.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 30824264      2.14%     66.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 51186075      3.55%     70.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                123166257      8.55%     78.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 68161636      4.73%     83.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 47264733      3.28%     86.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 36668750      2.55%     89.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                152556099     10.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1454140777                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses          353801341                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35355.537721                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35450.495050                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              353800095                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       44053000                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total           1439870042                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses          355034186                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35334.265176                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35459.890110                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              355032934                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       44238500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 1246                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits               337                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency     32224500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                 1252                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits               342                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency     32268500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses             909                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses             910                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               389219.026403                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               390146.081319                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses           353801341                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35355.537721                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35450.495050                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               353800095                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        44053000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses           355034186                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35334.265176                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35459.890110                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               355032934                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        44238500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  1246                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                337                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     32224500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                  1252                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                342                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     32268500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses              909                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses              910                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.349132                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            715.022199                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses          353801341                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35355.537721                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35450.495050                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.349698                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            716.180731                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses          355034186                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35334.265176                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35459.890110                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              353800095                       # number of overall hits
-system.cpu.icache.overall_miss_latency       44053000                       # number of overall miss cycles
+system.cpu.icache.overall_hits              355032934                       # number of overall hits
+system.cpu.icache.overall_miss_latency       44238500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 1246                       # number of overall misses
-system.cpu.icache.overall_mshr_hits               337                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     32224500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                 1252                       # number of overall misses
+system.cpu.icache.overall_mshr_hits               342                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     32268500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses             909                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses             910                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.sampled_refs                    909                       # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs                    910                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                715.022199                       # Cycle average of tags in use
-system.cpu.icache.total_refs                353800095                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                716.180731                       # Cycle average of tags in use
+system.cpu.icache.total_refs                355032934                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                        11703954                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                281582966                       # Number of branches executed
-system.cpu.iew.EXEC:nop                     129524501                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.553744                       # Inst execution rate
-system.cpu.iew.EXEC:refs                    770699454                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                  202312987                       # Number of stores executed
+system.cpu.idleCycles                        11330087                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                280332781                       # Number of branches executed
+system.cpu.iew.EXEC:nop                     129121920                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.560467                       # Inst execution rate
+system.cpu.iew.EXEC:refs                    767231280                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                  200922716                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                1532271545                       # num instructions consuming a value
-system.cpu.iew.WB:count                    2239351820                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.811403                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                1522686548                       # num instructions consuming a value
+system.cpu.iew.WB:count                    2225893734                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.811633                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                1243290213                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.527687                       # insts written-back per cycle
-system.cpu.iew.WB:sent                     2260914368                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts             21706879                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                16198055                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts             619677157                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                 45                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts          21613314                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts            233108974                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts          2613111960                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts             568386467                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          37669869                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts            2277546807                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 471616                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                1235862105                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.533830                       # insts written-back per cycle
+system.cpu.iew.WB:sent                     2246790117                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts             21706516                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                15735224                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts             619699188                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 43                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts          21567119                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts            233370796                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts          2608680423                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts             566308564                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          37529963                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts            2264549792                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 297607                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 28495                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles               91814713                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                777432                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 27486                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles               89450574                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                675659                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked       285764                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads        36261369                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses       212351                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked       161623                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads        33872925                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses       214320                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation      2343036                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads           14                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads    174010796                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     72203992                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents        2343036                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect      3386842                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect       18320037                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.184330                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.184330                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation      2995791                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads           17                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads    174032827                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores     72465814                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents        2995791                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect      3378494                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect       18328022                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.196281                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.196281                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu      1530874605     66.12%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult             97      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd           234      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp            19      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt           138      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult           16      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv            24      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     66.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead      578961528     25.01%     91.13% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite     205380015      8.87%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu      1521321100     66.08%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult             97      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd           232      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp            19      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt           138      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult           17      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv            24      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     66.08% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead      576616052     25.05%     91.13% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite     204142076      8.87%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total       2315216676                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt              13456867                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.005812                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total       2302079755                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt              12945104                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.005623                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu           2756939     20.49%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     20.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead          8882759     66.01%     86.50% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite         1817169     13.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu           2890284     22.33%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     22.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead          8361572     64.59%     86.92% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite         1693248     13.08%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples   1454140777                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.592154                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.762923                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples   1439870042                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.598811                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.750982                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0     566783737     38.98%     38.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1     267408405     18.39%     57.37% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2     245316156     16.87%     74.24% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3     135509048      9.32%     83.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4     112013237      7.70%     91.26% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5      72675996      5.00%     96.26% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6      44106984      3.03%     99.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7       8043729      0.55%     99.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8       2283485      0.16%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0     553825571     38.46%     38.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1     266666629     18.52%     56.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2     241255351     16.76%     73.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3     143700504      9.98%     83.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4     114580764      7.96%     91.68% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5      70398755      4.89%     96.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6      36702113      2.55%     99.12% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7      10651437      0.74%     99.85% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8       2088918      0.15%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total   1454140777                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.579442                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                 2483587414                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                2315216676                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                  45                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined       728311196                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued           1117432                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined    316872766                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total   1439870042                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.586328                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                 2479558460                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                2302079755                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  43                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined       726499267                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            996261                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined    330157127                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               353801377                       # ITB accesses
+system.cpu.itb.fetch_accesses               355034219                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   353801341                       # ITB hits
-system.cpu.itb.fetch_misses                        36                       # ITB misses
+system.cpu.itb.fetch_hits                   355034186                       # ITB hits
+system.cpu.itb.fetch_misses                        33                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -353,107 +351,98 @@ system.cpu.itb.write_accesses                       0                       # DT
 system.cpu.itb.write_acv                            0                       # DTB write access violations
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses         1884690                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.794335                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31398.574681                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              174907                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  59072651008                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.907196                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses           1709783                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  53684749213                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.907196                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses      1709783                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses           7277298                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34312.855500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31137.095153                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5437284                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   63136134500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.252843                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1840014                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  57292691000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.252843                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1840014                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         114023                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34289.699008                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31224.543680                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   3909814350                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           114023                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   3560316144                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       114023                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2367711                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2367711                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11849.162556                       # average number of cycles each access was blocked
+system.cpu.l2cache.ReadExReq_accesses         1884821                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34451.716970                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31263.065922                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits             1001550                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  30430202500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.468623                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            883271                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  27613759500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468623                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       883271                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses           7277260                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34300.261562                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.501409                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits               5456659                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   62447090500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.250177                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1820601                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56685325000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250177                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1820601                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3077872                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3077872                       # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10336.866902                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.526283                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs            27449                       # number of cycles access was blocked
+system.cpu.l2cache.avg_refs                  2.807813                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs             1698                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs    325247663                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs     17552000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            9161988                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34426.978644                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.038482                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                5612191                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   122208785508                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.387448                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              3549797                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses            9162081                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34349.737340                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.172773                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                6458209                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency    92877293000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.295115                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2703872                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 110977440213                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.387448                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         3549797                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency  84299084500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.295115                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2703872                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.481343                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.322273                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         15772.655639                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10560.226030                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses           9161988                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34426.978644                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.038482                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0                  0.484528                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.327269                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15877.018497                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10723.955560                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses           9162081                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34349.737340                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.172773                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               5612191                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  122208785508                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.387448                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             3549797                       # number of overall misses
+system.cpu.l2cache.overall_hits               6458209                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency   92877293000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.295115                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2703872                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 110977440213                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.387448                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        3549797                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency  84299084500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.295115                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2703872                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2708907                       # number of replacements
-system.cpu.l2cache.sampled_refs               2733538                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2693288                       # number of replacements
+system.cpu.l2cache.sampled_refs               2717930                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26332.881669                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 6905691                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          152081139500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1176798                       # number of writebacks
-system.cpu.memDep0.conflictingLoads         124506463                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         62743482                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads            619677157                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           233108974                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                       1465844731                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles         63989148                       # Number of cycles rename is blocking
+system.cpu.l2cache.tagsinuse             26600.974057                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7631439                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          148178401500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1171803                       # number of writebacks
+system.cpu.memDep0.conflictingLoads         134698193                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         69978801                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads            619699188                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           233370796                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                       1451200129                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles         52056982                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps     1376202963                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         5522165                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles         740664434                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents       19930963                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents        1000685                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups     3545348406                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts      2741098331                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands   2053584906                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles          528288951                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles        91814713                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles       29382701                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps         677381943                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles          830                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents         6212885                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles         741942603                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents       18353930                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents         492222                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups     3542299573                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts      2739870490                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands   2052189295                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles          529159748                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles        89450574                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles       27259412                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps         675986332                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles          723                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           48                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           59537135                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts           54988572                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           46                       # count of temporary serializing insts renamed
-system.cpu.timesIdled                          436319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled                          434261                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 28bd594f7..1d77692ce 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 47358dad4..1c00b7918 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:06:37
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:33:53
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +28,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2705279137000 because target called exit()
+Exiting @ tick 2663443716000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 713e89734..1b949665d 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1235575                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206704                       # Number of bytes of host memory used
-host_seconds                                  1472.82                       # Real time elapsed on the host
-host_tick_rate                             1836801554                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1370976                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 192892                       # Number of bytes of host memory used
+host_seconds                                  1327.36                       # Real time elapsed on the host
+host_tick_rate                             2006569980                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1819780127                       # Number of instructions simulated
-sim_seconds                                  2.705279                       # Number of seconds simulated
-sim_ticks                                2705279137000                       # Number of ticks simulated
+sim_seconds                                  2.663444                       # Number of seconds simulated
+sim_ticks                                2663443716000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   177812180000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency   177010400000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             158727823                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  104943266000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.012448                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             2000679                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  98941229000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.012448                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        2000679                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   63798266000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  58130306000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30657.334367                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               596101072                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    282755446000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.015237                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9223093                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 26428.412638                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    240808666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 255086167000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.015237                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9223093                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 213473464000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.996035                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4079.758997                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.995973                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4079.504248                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30657.334367                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 26428.412638                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              596101072                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   282755446000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.015237                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9223093                       # number of overall misses
+system.cpu.dcache.overall_hits              596212431                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   240808666000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              9111734                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 255086167000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.015237                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9223093                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 213473464000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                9107638                       # number of replacements
 system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4079.758997                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4079.504248                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            40990273000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2365949                       # number of writebacks
+system.cpu.dcache.warmup_cycle            40989969000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3058802                       # number of writebacks
 system.cpu.dtb.data_accesses                611922547                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                    605324165                       # DTB hits
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses              802                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.298761                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            611.862910                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.299002                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            612.356766                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1826378510                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      1                       # number of replacements
 system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                611.862910                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                612.356766                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1826377708                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,37 +164,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses         1889320                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              168921                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  89460748000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.910592                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses           1720399                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  68815960000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.910592                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses      1720399                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits             1000087                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  46240116000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.470663                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            889233                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35569320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.470663                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       889233                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           7223216                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5396262                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   95001608000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.252928                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1826954                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  73078160000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.252928                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1826954                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         111359                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   5786716000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           111359                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   4454360000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       111359                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2365949                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2365949                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               5415352                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   94008928000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.250285                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1807864                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72314560000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250285                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1807864                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3058802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3058802                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.515193                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.790701                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                5565183                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   184462356000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.389283                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              3547353                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                6415439                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   140249044000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.295977                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2697097                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 141894120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.389283                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         3547353                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 107883880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.295977                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2697097                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.466649                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.320836                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         15291.153152                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10513.160578                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.467301                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.327380                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15312.508302                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10727.578894                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9112536                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               5565183                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  184462356000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.389283                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             3547353                       # number of overall misses
+system.cpu.l2cache.overall_hits               6415439                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  140249044000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.295977                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2697097                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 141894120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.389283                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        3547353                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 107883880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.295977                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2697097                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2701645                       # number of replacements
-system.cpu.l2cache.sampled_refs               2726277                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2686269                       # number of replacements
+system.cpu.l2cache.sampled_refs               2710912                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             25804.313731                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 6857112                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          596452524000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1175830                       # number of writebacks
+system.cpu.l2cache.tagsinuse             26040.087196                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7565346                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          582065656000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1170923                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       5410558274                       # number of cpu cycles simulated
+system.cpu.numCycles                       5326887432                       # number of cpu cycles simulated
 system.cpu.num_insts                       1819780127                       # Number of instructions executed
 system.cpu.num_refs                         613169725                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              29                       # Number of system calls
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 58d6d5f57..6b81a05a4 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
index 04bd91fa3..be9f97c93 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 14:05:19
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:06:16
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -31,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2473217439000 because target called exit()
+Exiting @ tick 2431420115000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 92d034701..5855e152d 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1470110                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211484                       # Number of bytes of host memory used
-host_seconds                                  1158.83                       # Real time elapsed on the host
-host_tick_rate                             2134239180                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1373516                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197324                       # Number of bytes of host memory used
+host_seconds                                  1240.32                       # Real time elapsed on the host
+host_tick_rate                             1960310324                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1703605163                       # Number of instructions simulated
-sim_seconds                                  2.473217                       # Number of seconds simulated
-sim_ticks                                2473217439000                       # Number of ticks simulated
+sim_seconds                                  2.431420                       # Number of seconds simulated
+sim_ticks                                2431420115000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          482384248                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24630.043664                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21630.043664                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24514.094748                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.094748                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              475158152                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   177979060000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency   177141202000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              7226096                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156300772000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 155462914000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         7226096                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         172586108                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 52467.599202                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49467.599202                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             170586898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  104893749000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.011584                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1999210                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  98896119000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011584                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1999210                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             170696959                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  58156775000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                  70.854389                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           654970356                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30662.702029                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 27662.702029                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               645745050                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    282872809000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.014085                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9225306                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 26435.430315                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               645855111                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    240965424000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               9115245                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 255196891000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.014085                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9225306                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 213619689000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9115245                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997054                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4083.932190                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.997003                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4083.724785                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          654970356                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30662.702029                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 27662.702029                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 26435.430315                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23435.430315                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              645745050                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   282872809000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.014085                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9225306                       # number of overall misses
+system.cpu.dcache.overall_hits              645855111                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   240965424000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              9115245                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 255196891000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.014085                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9225306                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 213619689000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9115245                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                9111149                       # number of replacements
 system.cpu.dcache.sampled_refs                9115245                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4083.932190                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4083.724785                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                645855111                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            25923011000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2365751                       # number of writebacks
+system.cpu.dcache.warmup_cycle            25922969000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3061986                       # number of writebacks
 system.cpu.dtb.accesses                             0                       # DTB accesses
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
@@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses              638                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.251186                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            514.428387                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.251403                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            514.872908                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1544565415                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      7                       # number of replacements
 system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                514.428387                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                514.872908                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1544564777                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,37 +150,28 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses         1889149                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              168141                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  89492416000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.910996                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses           1721008                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  68840320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.910996                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses      1721008                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              999241                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  46275216000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.471063                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            889908                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           7226734                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5397220                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   95134728000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.253159                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1829514                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  73180560000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.253159                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1829514                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         110061                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51957.950591                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   5718544000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           110061                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   4402440000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       110061                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2365751                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2365751                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               5417169                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   94097380000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.250399                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1809565                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  72382600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250399                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1809565                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3061986                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3061986                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.511929                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.788539                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            9115883                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                5565361                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   184627144000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.389487                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              3550522                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                6416410                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   140372596000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.296129                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2699473                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 142020880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.389487                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         3550522                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 107978920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.296129                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2699473                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.457042                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.333046                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         14976.359071                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10913.242343                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.458608                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.338955                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15027.674424                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11106.876723                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9115883                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               5565361                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  184627144000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.389487                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             3550522                       # number of overall misses
+system.cpu.l2cache.overall_hits               6416410                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  140372596000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.296129                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2699473                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 142020880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.389487                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        3550522                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 107978920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.296129                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2699473                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2702712                       # number of replacements
-system.cpu.l2cache.sampled_refs               2729930                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2687070                       # number of replacements
+system.cpu.l2cache.sampled_refs               2714388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             25889.601414                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 6857391                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          555158623000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1177576                       # number of writebacks
+system.cpu.l2cache.tagsinuse             26134.551147                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7569176                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          538044067000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1171981                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4946434878                       # number of cpu cycles simulated
+system.cpu.numCycles                       4862840230                       # number of cpu cycles simulated
 system.cpu.num_insts                       1703605163                       # Number of instructions executed
 system.cpu.num_refs                         660773876                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 3936b82c4..3cfbdc174 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
index 006c94330..0188b7f37 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:20:12
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:20:23
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:23:28
+M5 executing on phenom
 command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -31,4 +29,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 5965358694000 because target called exit()
+Exiting @ tick 5923548078000 because target called exit()
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index a660251b7..da5e11c9b 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 828534                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210088                       # Number of bytes of host memory used
-host_seconds                                  5616.34                       # Real time elapsed on the host
-host_tick_rate                             1062144168                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1201976                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 195452                       # Number of bytes of host memory used
+host_seconds                                  3871.40                       # Real time elapsed on the host
+host_tick_rate                             1530079593                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  4653327945                       # Number of instructions simulated
-sim_seconds                                  5.965359                       # Number of seconds simulated
-sim_ticks                                5965358694000                       # Number of ticks simulated
+sim_seconds                                  5.923548                       # Number of seconds simulated
+sim_ticks                                5923548078000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses         1239184749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24735.540403                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21735.540403                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits             1231961899                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   178661098000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency   177808540000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.005829                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses              7222850                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156992548000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses         7222850                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses         438528337                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 52475.088886                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49475.088886                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             436528587                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  104937059000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.004560                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses             1999750                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  98937809000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.004560                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses        1999750                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             436638510                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   63869078000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.004309                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses             1889827                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency  58199597000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.004309                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses        1889827                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses          1677713086                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30750.347733                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 27750.347733                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits              1668490486                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    283598157000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.005497                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               9222600                       # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 26521.034159                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits              1668600409                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    241677618000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.005432                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               9112677                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 255930357000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.005497                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          9222600                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 214339587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.005432                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          9112677                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.997251                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           4084.741632                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.997232                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4084.662246                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses         1677713086                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30750.347733                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 27750.347733                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 26521.034159                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits             1668490486                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   283598157000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.005497                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              9222600                       # number of overall misses
+system.cpu.dcache.overall_hits             1668600409                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   241677618000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.005432                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              9112677                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 255930357000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.005497                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         9222600                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 214339587000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.005432                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         9112677                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                9108581                       # number of replacements
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4084.741632                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4084.662246                       # Cycle average of tags in use
 system.cpu.dcache.total_refs               1668600409                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            58862918000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                  2365669                       # number of writebacks
+system.cpu.dcache.warmup_cycle            58862779000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                  3053391                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         4013232927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
@@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses              675                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.271287                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            555.595041                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.271344                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            555.713137                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         4013232927                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                     10                       # number of replacements
 system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                555.595041                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                555.713137                       # Cycle average of tags in use
 system.cpu.icache.total_refs               4013232252                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -132,37 +132,28 @@ system.cpu.idle_fraction                            0                       # Pe
 system.cpu.l2cache.ReadExReq_accesses         1889827                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits              167830                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency  89543844000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate       0.911193                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses           1721997                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  68879880000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.911193                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses      1721997                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits              999077                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency  46319000000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.471339                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses            890750                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  35630000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471339                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses       890750                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses           7223525                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits               5376631                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency   96038488000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.255678                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1846894                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  73875760000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.255678                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1846894                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses         109923                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51961.682268                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   5711784000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses           109923                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   4396920000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses       109923                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses         2365669                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits             2365669                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits               5396930                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency   94982940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.252868                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1826595                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency  73063800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.252868                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1826595                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses         3053391                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits             3053391                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.486980                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.758083                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses            9113352                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                5544461                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency   185582332000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.391611                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              3568891                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                6396007                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency   141301940000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.298172                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              2717345                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 142755640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.391611                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         3568891                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 108693800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.298172                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         2717345                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.472057                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.330298                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0         15468.376741                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10823.217602                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.472376                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.336564                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0         15478.805498                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         11028.544571                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses           9113352                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits               5544461                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency  185582332000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.391611                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             3568891                       # number of overall misses
+system.cpu.l2cache.overall_hits               6396007                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency  141301940000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.298172                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             2717345                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 142755640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.391611                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        3568891                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 108693800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.298172                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        2717345                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements               2721965                       # number of replacements
-system.cpu.l2cache.sampled_refs               2748168                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements               2706631                       # number of replacements
+system.cpu.l2cache.sampled_refs               2732923                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             26291.594343                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 6834640                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          1346606710000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                 1180493                       # number of writebacks
+system.cpu.l2cache.tagsinuse             26507.350069                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7537629                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          1324806325000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                 1174631                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                      11930717388                       # number of cpu cycles simulated
+system.cpu.numCycles                      11847096156                       # number of cpu cycles simulated
 system.cpu.num_insts                       4653327945                       # Number of instructions executed
 system.cpu.num_refs                        1677713086                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              46                       # Number of system calls
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 72f88064b..107f17441 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -191,7 +191,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 78d80c7fd..b14e624c0 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:18:42
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:52:34
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 98337080000 because target called exit()
+122 123 124 Exiting @ tick 98335161000 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 4e98786e0..3c9f3dbf4 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  33745                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211108                       # Number of bytes of host memory used
-host_seconds                                  2723.45                       # Real time elapsed on the host
-host_tick_rate                               36107563                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  54763                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197304                       # Number of bytes of host memory used
+host_seconds                                  1678.20                       # Real time elapsed on the host
+host_tick_rate                               58595727                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
-sim_seconds                                  0.098337                       # Number of seconds simulated
-sim_ticks                                 98337080000                       # Number of ticks simulated
+sim_seconds                                  0.098335                       # Number of seconds simulated
+sim_ticks                                 98335161000                       # Number of ticks simulated
 system.cpu.AGEN-Unit.agens                   26537108                       # Number of Address Generations
 system.cpu.Branch-Predictor.BTBHitPct       64.034182                       # BTB Hit Percentage
 system.cpu.Branch-Predictor.BTBHits           5496951                       # Number of BTB hits
@@ -27,11 +27,11 @@ system.cpu.Execution-Unit.predictedNotTakenIncorrect       409064
 system.cpu.Execution-Unit.predictedTakenIncorrect      1911977                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.Mult-Div-Unit.multiplies            458252                       # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses    185972267                       # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads     117544906                       # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses    185972268                       # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads     117544907                       # Number of Reads from Register File
 system.cpu.RegFile-Manager.regFileWrites     68427361                       # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards        2843091                       # Number of Registers Read Through Forwarding Logic
-system.cpu.activity                         95.460360                       # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards        2843090                       # Number of Registers Read Through Forwarding Logic
+system.cpu.activity                         95.462227                       # Percentage of cycles cpu is active
 system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
 system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
 system.cpu.comInts                           43625545                       # Number of Integer instructions committed
@@ -42,28 +42,28 @@ system.cpu.comStores                          6502695                       # Nu
 system.cpu.committedInsts                    91903056                       # Number of Instructions Simulated (Per-Thread)
 system.cpu.committedInsts_total              91903056                       # Number of Instructions Simulated (Total)
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.cpi                               2.140018                       # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total                         2.140018                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               2.139976                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total                         2.139976                       # CPI: Total CPI of All Threads
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48524.210526                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits               19995723                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       24487000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency       24486000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  475                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     23049500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     23049000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6499339                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      99174500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000271                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1764                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     93882500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000271                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1764                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55595.537757                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52592.105263                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      97181000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     91931000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
@@ -73,42 +73,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55230.683341                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26495062                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       123661500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 54730.994152                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51722.896986                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26495078                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       121667000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2239                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  2223                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    116932000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    114980000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2239                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.352018                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1441.865798                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.352016                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1441.857733                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55230.683341                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54730.994152                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51722.896986                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26495062                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      123661500                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               26495078                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      121667000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2239                       # number of overall misses
+system.cpu.dcache.overall_misses                 2223                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    116932000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    114980000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2239                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1441.865798                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1441.857733                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      104                       # number of writebacks
+system.cpu.dcache.writebacks                      107                       # number of writebacks
 system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                     26497301                       # DTB hits
@@ -126,50 +126,50 @@ system.cpu.dtb.write_acv                            0                       # DT
 system.cpu.dtb.write_hits                     6501103                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.icache.ReadReq_accesses          101762751                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27218.266790                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits              101754085                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      235873500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_avg_miss_latency 27216.197508                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.134662                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              101754083                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      235910000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000085                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                 8666                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits                89                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    205719500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                 8668                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits                91                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    205720500                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000084                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            8577                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets         2000                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               11863.598578                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               11863.598344                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets         2000                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses           101762751                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27218.266790                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072                       # average overall mshr miss latency
-system.cpu.icache.demand_hits               101754085                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       235873500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_avg_miss_latency 27216.197508                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23985.134662                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               101754083                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       235910000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000085                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                  8666                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                 89                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    205719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                  8668                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                 91                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    205720500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             8577                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.697638                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1428.763035                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.697636                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1428.759296                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          101762751                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27218.266790                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 27216.197508                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23985.134662                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits              101754085                       # number of overall hits
-system.cpu.icache.overall_miss_latency      235873500                       # number of overall miss cycles
+system.cpu.icache.overall_hits              101754083                       # number of overall hits
+system.cpu.icache.overall_miss_latency      235910000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000085                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                 8666                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                89                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    205719500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                 8668                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                91                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    205720500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            8577                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -177,13 +177,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   6743                       # number of replacements
 system.cpu.icache.sampled_refs                   8577                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1428.763035                       # Cycle average of tags in use
-system.cpu.icache.total_refs                101754085                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1428.759296                       # Cycle average of tags in use
+system.cpu.icache.total_refs                101754083                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         8928298                       # Number of cycles cpu's stages were not processed
-system.cpu.ipc                               0.467286                       # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total                         0.467286                       # IPC: Total IPC of All Threads
+system.cpu.idleCycles                         8924453                       # Number of cycles cpu's stages were not processed
+system.cpu.ipc                               0.467295                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total                         0.467295                       # IPC: Total IPC of All Threads
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
@@ -201,104 +201,96 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     91275000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1748                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     69930000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1748                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.318235                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.807201                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency     89916500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     68890000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              9052                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52167.972576                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  5989                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     159790000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency     159790500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate         0.338378                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                3063                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency    122581500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338378                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3063                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52250                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       836000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               16                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       641000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.912000                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.916906                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses              10800                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52185.616296                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   5989                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      251065000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.445463                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4811                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 52185.370951                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.942529                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                   6015                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      249707000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.443056                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4785                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    192511500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.445463                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4811                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    191471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.443056                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4785                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0                  0.063287                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000419                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2073.775621                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            13.721424                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0                  0.063286                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2073.767582                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.791341                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             10800                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52185.616296                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52185.370951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.942529                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  5989                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     251065000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.445463                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4811                       # number of overall misses
+system.cpu.l2cache.overall_hits                  6015                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     249707000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.443056                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4785                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    192511500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.445463                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4811                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    191471500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.443056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4785                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3125                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3129                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2087.497045                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    5975                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2091.558923                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    5998                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                        196674161                       # number of cpu cycles simulated
-system.cpu.runCycles                        187745863                       # Number of cycles cpu stages are processed.
+system.cpu.numCycles                        196670323                       # number of cpu cycles simulated
+system.cpu.runCycles                        187745870                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles                94911362                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles                94907524                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-0.runCycles                101762799                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization              51.741824                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles               104513647                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization              51.742834                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles               104509809                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-1.runCycles                 92160514                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization              46.859493                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles               103181677                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.utilization              46.860407                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles               103177839                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-2.runCycles                 93492484                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization              47.536740                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles               170137030                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization              47.537667                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles               170133192                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-3.runCycles                 26537131                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization              13.492942                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles               104771105                       # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization              13.493206                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles               104767267                       # Number of cycles 0 instructions are processed.
 system.cpu.stage-4.runCycles                 91903056                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization              46.728587                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles                     196674161                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization              46.729499                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles                     196670323                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index d1980c8dc..bcd7db1f0 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -358,7 +358,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
index 9e4298349..64c5673b1 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,12 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:11:51
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:34:48
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -30,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 40700936000 because target called exit()
+122 123 124 Exiting @ tick 40701237000 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 88a37a0c5..434f6f061 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,295 +1,295 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 126678                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211676                       # Number of bytes of host memory used
-host_seconds                                   664.52                       # Real time elapsed on the host
-host_tick_rate                               61249065                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 172806                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197872                       # Number of bytes of host memory used
+host_seconds                                   487.13                       # Real time elapsed on the host
+host_tick_rate                               83552440                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_seconds                                  0.040701                       # Number of seconds simulated
-sim_ticks                                 40700936000                       # Number of ticks simulated
+sim_ticks                                 40701237000                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                 11915731                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              15874516                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 11915545                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              15874334                       # Number of BTB lookups
 system.cpu.BPredUnit.RASInCorrect                1218                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect            1889856                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           14601933                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 19578482                       # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect            1889899                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           14602096                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 19578655                       # Number of BP lookups
 system.cpu.BPredUnit.usedRAS                  1736849                       # Number of times the RAS was used to get a target.
 system.cpu.commit.COM:branches               10240685                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           2865019                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events           2864912                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     73200115                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     1.255504                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.951469                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     73200571                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     1.255496                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.951465                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     35882998     49.02%     49.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     18421131     25.17%     74.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      7399939     10.11%     84.30% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      3793003      5.18%     89.48% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2033143      2.78%     92.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5      1324637      1.81%     94.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       734587      1.00%     95.07% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       745658      1.02%     96.09% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      2865019      3.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     35883667     49.02%     49.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     18420857     25.16%     74.19% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      7399798     10.11%     84.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      3793136      5.18%     89.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2033346      2.78%     92.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5      1324316      1.81%     94.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       734839      1.00%     95.07% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       745700      1.02%     96.09% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      2864912      3.91%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     73200115                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total     73200571                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                  91903055                       # Number of instructions committed
 system.cpu.commit.COM:loads                  20034413                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                   26537108                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts           1876719                       # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts           1876760                       # The number of times a branch was mispredicted
 system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts        56257070                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        56257975                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.967001                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.967001                       # CPI: Total CPI of All Threads
+system.cpu.cpi                               0.967008                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.967008                       # CPI: Total CPI of All Threads
 system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_hits               11                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses           23361768                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30148.648649                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32165.686275                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits               23360880                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency       26772000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_accesses           23361980                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30151.634724                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32163.725490                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               23361093                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency       26744500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000038                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses                  888                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits               378                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency     16404500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses                  887                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits               377                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency     16403500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             510                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35665.614165                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35983.686319                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6493027                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     288035500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.001242                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                8076                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits             6329                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency     62863500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1747                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 35569.269207                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35483.256351                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               6493098                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     284732000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.001231                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                8005                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits             6273                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency     61457000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1732                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs         1500                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs               13315.768510                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               13315.879572                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs         1500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            29862871                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35119.087461                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35120.957023                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                29853907                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       314807500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.000300                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  8964                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits               6707                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     79268000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.000076                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2257                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses            29863083                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35028.846154                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34728.144514                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                29854191                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       311476500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.000298                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                  8892                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits               6650                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency     77860500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.000075                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses             2242                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.356506                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1460.250343                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses           29862871                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35119.087461                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35120.957023                       # average overall mshr miss latency
+system.cpu.dcache.occ_%::0                   0.356508                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1460.254824                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses           29863083                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35028.846154                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34728.144514                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               29853907                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      314807500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.000300                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 8964                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits              6707                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     79268000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.000076                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2257                       # number of overall MSHR misses
+system.cpu.dcache.overall_hits               29854191                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      311476500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.000298                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                 8892                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits              6650                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency     77860500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.000075                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses            2242                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    160                       # number of replacements
 system.cpu.dcache.sampled_refs                   2242                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1460.250343                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 29853953                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1460.254824                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 29854202                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      106                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles        4195548                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          13275                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved       3138319                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts       162326104                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          39347421                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           29437279                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         8092915                       # Number of cycles decode is squashing
+system.cpu.dcache.writebacks                      109                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles        4195761                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          13279                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved       3138343                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts       162326891                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          39347906                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           29437041                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         8093015                       # Number of cycles decode is squashing
 system.cpu.decode.DECODE:SquashedInsts          48049                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles         219867                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                 31798312                       # DTB accesses
+system.cpu.decode.DECODE:UnblockCycles         219863                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                 31798533                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                     31419824                       # DTB hits
-system.cpu.dtb.data_misses                     378488                       # DTB misses
+system.cpu.dtb.data_hits                     31420024                       # DTB hits
+system.cpu.dtb.data_misses                     378509                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 24587008                       # DTB read accesses
+system.cpu.dtb.read_accesses                 24587243                       # DTB read accesses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                     24209579                       # DTB read hits
-system.cpu.dtb.read_misses                     377429                       # DTB read misses
-system.cpu.dtb.write_accesses                 7211304                       # DTB write accesses
+system.cpu.dtb.read_hits                     24209793                       # DTB read hits
+system.cpu.dtb.read_misses                     377450                       # DTB read misses
+system.cpu.dtb.write_accesses                 7211290                       # DTB write accesses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                     7210245                       # DTB write hits
+system.cpu.dtb.write_hits                     7210231                       # DTB write hits
 system.cpu.dtb.write_misses                      1059                       # DTB write misses
-system.cpu.fetch.Branches                    19578482                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                  19042269                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      49581999                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                482446                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                      167417229                       # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles                 2029251                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.240516                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles           19042269                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches           13652580                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        2.056675                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           81293030                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.059429                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.087442                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    19578655                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                  19042384                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      49581925                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                482421                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                      167418269                       # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles                 2029286                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.240517                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles           19042384                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches           13652394                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        2.056673                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           81293586                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.059428                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.087450                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 50753371     62.43%     62.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3139837      3.86%     66.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1896166      2.33%     68.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3230989      3.97%     72.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4381492      5.39%     77.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1498123      1.84%     79.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1855484      2.28%     82.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1657938      2.04%     84.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 12879630     15.84%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 50754116     62.43%     62.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3139628      3.86%     66.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1895979      2.33%     68.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3231029      3.97%     72.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4381369      5.39%     77.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1498108      1.84%     79.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1855702      2.28%     82.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1657872      2.04%     84.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 12879783     15.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             81293030                       # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses           19042269                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15754.189443                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11879.245840                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               19031110                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency      175801000                       # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total             81293586                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses           19042384                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15742.896836                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11872.070120                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               19031227                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      175643500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000586                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                11159                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits              1002                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency    120657500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses                11157                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits              1003                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency    120549000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000533                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           10157                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses           10154                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                1873.694004                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                1874.259110                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            19042269                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15754.189443                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11879.245840                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                19031110                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency       175801000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses            19042384                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15742.896836                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11872.070120                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                19031227                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       175643500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000586                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 11159                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits               1002                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency    120657500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses                 11157                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits               1003                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    120549000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000533                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            10157                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses            10154                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.756087                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1548.466977                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses           19042269                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15754.189443                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11879.245840                       # average overall mshr miss latency
+system.cpu.icache.occ_%::0                   0.756089                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1548.470149                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses           19042384                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15742.896836                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11872.070120                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               19031110                       # number of overall hits
-system.cpu.icache.overall_miss_latency      175801000                       # number of overall miss cycles
+system.cpu.icache.overall_hits               19031227                       # number of overall hits
+system.cpu.icache.overall_miss_latency      175643500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000586                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                11159                       # number of overall misses
-system.cpu.icache.overall_mshr_hits              1002                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency    120657500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses                11157                       # number of overall misses
+system.cpu.icache.overall_mshr_hits              1003                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    120549000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000533                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           10157                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses           10154                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                   8241                       # number of replacements
-system.cpu.icache.sampled_refs                  10157                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                   8238                       # number of replacements
+system.cpu.icache.sampled_refs                  10154                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1548.466977                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 19031110                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1548.470149                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 19031227                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                          108843                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                 12932923                       # Number of branches executed
-system.cpu.iew.EXEC:nop                      12752202                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     1.252024                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     31851727                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    7212953                       # Number of stores executed
+system.cpu.idleCycles                          108889                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                 12932789                       # Number of branches executed
+system.cpu.iew.EXEC:nop                      12752151                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     1.252018                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     31851951                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    7212939                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  91350917                       # num instructions consuming a value
-system.cpu.iew.WB:count                     100121723                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.722506                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  91351431                       # num instructions consuming a value
+system.cpu.iew.WB:count                     100121785                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.722504                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  66001625                       # num instructions producing a value
-system.cpu.iew.WB:rate                       1.229968                       # insts written-back per cycle
-system.cpu.iew.WB:sent                      100959925                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts              2058548                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                  308035                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              33906352                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts                439                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts           1495689                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts             10659868                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts           148158966                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              24638774                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2167496                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts             101917138                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                 147063                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  66001783                       # num instructions producing a value
+system.cpu.iew.WB:rate                       1.229960                       # insts written-back per cycle
+system.cpu.iew.WB:sent                      100960101                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts              2058583                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                  308073                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              33906754                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                436                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts           1495766                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts             10659940                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts           148159865                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              24639012                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2167407                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             101917357                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                 147057                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                   222                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                8092915                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                184741                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                   229                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                8093015                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                184742                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread.0.cacheBlocked            1                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          837967                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         2533                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads          837974                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         2531                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       262394                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads         9832                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     13871939                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores      4157173                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents         262394                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       456488                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect        1602060                       # Number of branches that were predicted taken incorrectly
-system.cpu.ipc                               1.034125                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.034125                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation       262379                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads         9827                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads     13872341                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores      4157245                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents         262379                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       456408                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect        1602175                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               1.034117                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.034117                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        64580885     62.05%     62.05% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult         474250      0.46%     62.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        64580956     62.05%     62.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult         474234      0.46%     62.50% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     62.50% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2786793      2.68%     65.18% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd       2786797      2.68%     65.18% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCmp        114549      0.11%     65.29% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2387015      2.29%     67.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2387018      2.29%     67.58% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatMult       305140      0.29%     67.88% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatDiv        754986      0.73%     68.60% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatSqrt          323      0.00%     68.60% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       25334190     24.34%     92.94% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       7346496      7.06%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       25334340     24.34%     92.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       7346414      7.06%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total        104084634                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt               1605159                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.015422                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total        104084764                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt               1605421                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.015424                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu            233517     14.55%     14.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu            233590     14.55%     14.55% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     14.55% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     14.55% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatAdd             339      0.02%     14.57% # attempts to use FU when none available
@@ -298,42 +298,42 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt            3702      0.23%     14.80% # at
 system.cpu.iq.ISSUE:fu_full::FloatMult           2371      0.15%     14.95% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatDiv          538253     33.53%     48.48% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     48.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           750460     46.75%     95.23% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite           76517      4.77%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead           750644     46.76%     95.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite           76522      4.77%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     81293030                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     1.280364                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.539599                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     81293586                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     1.280356                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.539590                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      34992329     43.04%     43.04% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      18915944     23.27%     66.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2      11753054     14.46%     80.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       6613669      8.14%     88.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       5112903      6.29%     95.20% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       2406334      2.96%     98.16% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6       1201307      1.48%     99.63% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        249469      0.31%     99.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         48021      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      34992440     43.04%     43.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      18916491     23.27%     66.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2      11753286     14.46%     80.77% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       6613191      8.13%     88.91% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       5113111      6.29%     95.20% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       2406044      2.96%     98.16% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6       1201508      1.48%     99.63% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        249704      0.31%     99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         47811      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     81293030                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     1.278652                       # Inst issue rate
-system.cpu.iq.iqInstsAdded                  135406325                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                 104084634                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded                 439                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined        50573904                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued            302099                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved             50                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined     47258027                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     81293586                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     1.278644                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                  135407278                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                 104084764                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                 436                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined        50574577                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued            302079                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved             47                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined     47259225                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                19042340                       # ITB accesses
+system.cpu.itb.fetch_accesses                19042455                       # ITB accesses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    19042269                       # ITB hits
+system.cpu.itb.fetch_hits                    19042384                       # ITB hits
 system.cpu.itb.fetch_misses                        71                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,103 +344,95 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.l2cache.ReadExReq_accesses            1732                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34688.510393                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31520.207852                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     60080500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1732                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     54593000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1732                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses             10667                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34283.465725                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.788761                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34699.413490                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31528.152493                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits                  27                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency     59162500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.984411                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1705                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     53755500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.984411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1705                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses             10664                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34281.213192                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.566549                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_hits                  7268                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency     116529500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.318646                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses                3399                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    105647000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.318646                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses           3399                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             15                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34166.666667                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       512500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               15                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       465000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           15                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             106                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 106                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_miss_latency     116419000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.318455                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                3396                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    105553000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.318455                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses           3396                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses             109                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 109                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  2.094427                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.100462                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses              12399                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34420.190996                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.779770                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   7268                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      176610000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.413824                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 5131                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses              12396                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34420.995883                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.837091                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                   7295                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      175581500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.411504                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 5101                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    160240000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.413824                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            5131                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    159308500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.411504                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            5101                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.070268                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000413                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2302.538330                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            13.547355                       # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses             12399                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34420.190996                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.779770                       # average overall mshr miss latency
+system.cpu.l2cache.occ_%::1                  0.000537                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2302.534301                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.609654                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses             12396                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34420.995883                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.837091                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  7268                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     176610000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.413824                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                5131                       # number of overall misses
+system.cpu.l2cache.overall_hits                  7295                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     175581500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.411504                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                5101                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    160240000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.413824                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           5131                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    159308500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.411504                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           5101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3463                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3464                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2316.085685                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    7253                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2320.143954                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    7276                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.memDep0.conflictingLoads          17615087                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5052814                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             33906352                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10659868                       # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles                         81401873                       # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles          1958439                       # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads          17616969                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5053323                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             33906754                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10659940                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                         81402475                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles          1958550                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps       68427361                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         1204670                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          40603212                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents         943778                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups      202469078                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts       157094553                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands    115390079                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           28386104                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         8092915                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        2247194                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps          46962718                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles         5166                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts          474                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts            4950472                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts          463                       # count of temporary serializing insts renamed
+system.cpu.rename.RENAME:IQFullEvents         1204707                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          40603552                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents         943829                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups      202471233                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts       157096154                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands    115391431                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           28385991                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         8093015                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        2247276                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps          46964070                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles         5202                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts          471                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts            4950569                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts          460                       # count of temporary serializing insts renamed
 system.cpu.timesIdled                            2416                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
 
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 3a1e6de05..81bd24631 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
index 258e66688..638d6c514 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:58:58
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:52
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -30,4 +26,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 118742021000 because target called exit()
+122 123 124 Exiting @ tick 118740049000 because target called exit()
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index b08531811..fb91662b2 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1269659                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 210612                       # Number of bytes of host memory used
-host_seconds                                    72.38                       # Real time elapsed on the host
-host_tick_rate                             1640438984                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1097596                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196804                       # Number of bytes of host memory used
+host_seconds                                    83.73                       # Real time elapsed on the host
+host_tick_rate                             1418103765                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    91903056                       # Number of instructions simulated
-sim_seconds                                  0.118742                       # Number of seconds simulated
-sim_ticks                                118742021000                       # Number of ticks simulated
+sim_seconds                                  0.118740                       # Number of seconds simulated
+sim_ticks                                118740049000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211                       # average ReadReq mshr miss latency
@@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency     22949000                       #
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits               6499339                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      98784000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000271                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1764                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     93492000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000271                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1764                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      96796000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     91552000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
@@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55005.806163                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                26495062                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       123158000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 54507.422402                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                26495078                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       121170000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  2239                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  2223                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    116441000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    114501000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             2239                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0                   0.352059                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1442.035674                       # Average occupied blocks per context
+system.cpu.dcache.occ_%::0                   0.352058                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           1442.028823                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55005.806163                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54507.422402                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               26495062                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      123158000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               26495078                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      121170000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 2239                       # number of overall misses
+system.cpu.dcache.overall_misses                 2223                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    116441000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    114501000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            2239                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1442.035674                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1442.028823                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                      104                       # number of writebacks
+system.cpu.dcache.writebacks                      107                       # number of writebacks
 system.cpu.dtb.data_accesses                 26497334                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                     26497301                       # DTB hits
@@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses             8510                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.692403                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1418.041181                       # Average occupied blocks per context
+system.cpu.icache.occ_%::0                   0.692401                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0           1418.037996                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
@@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   6681                       # number of replacements
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1418.041181                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1418.037996                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -164,12 +164,13 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     90896000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1748                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     69920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1748                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency     89544000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     68880000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              8985                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
@@ -180,20 +181,11 @@ system.cpu.l2cache.ReadReq_misses                3043                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency    121720000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338676                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           3043                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses             16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency       832000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses               16                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       640000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses             104                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits                 104                       # number of Writeback hits
+system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  1.909179                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.914120                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -202,44 +194,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses              10733                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   5942                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      249132000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.446380                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4791                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                   5968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      247780000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.443958                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4765                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    191640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.446380                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4791                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    190600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.443958                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4765                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.062752                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000419                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2056.260143                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            13.724287                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::1                  0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2056.253411                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.795183                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  5942                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     249132000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.446380                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4791                       # number of overall misses
+system.cpu.l2cache.overall_hits                  5968                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     247780000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.443958                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4765                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    191640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.446380                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4791                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    190600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.443958                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4765                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  3105                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2069.984431                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    5928                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2074.048594                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    5951                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        237484042                       # number of cpu cycles simulated
+system.cpu.numCycles                        237480098                       # number of cpu cycles simulated
 system.cpu.num_insts                         91903056                       # Number of instructions executed
 system.cpu.num_refs                          26537141                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             389                       # Number of system calls
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
index 43ac38afd..efc2b1daf 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
index a3b84a071..931f30561 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:52:30
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:54:23
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:05:16
+M5 executing on phenom
 command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -30,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 232028062000 because target called exit()
+122 123 124 Exiting @ tick 232027671000 because target called exit()
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 156b8dc2a..ea6f10d3a 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1713926                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214560                       # Number of bytes of host memory used
-host_seconds                                   108.72                       # Real time elapsed on the host
-host_tick_rate                             2134224518                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1260082                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 200384                       # Number of bytes of host memory used
+host_seconds                                   147.87                       # Real time elapsed on the host
+host_tick_rate                             1569082964                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   186333855                       # Number of instructions simulated
 sim_seconds                                  0.232028                       # Number of seconds simulated
-sim_ticks                                232028062000                       # Number of ticks simulated
+sim_ticks                                232027671000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           29640180                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217                       # average ReadReq mshr miss latency
@@ -19,15 +19,15 @@ system.cpu.dcache.ReadReq_mshr_miss_latency     34134000                       #
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             690                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          12386694                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits              12385593                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      61656000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              12385594                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses                1101                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     58353000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses           1101                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs               23477.700559                       # Average number of references to valid blocks.
@@ -37,39 +37,39 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            42026874                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54639.865997                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51639.865997                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                42025083                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency        97860000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 54451.396648                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51451.396648                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                42025084                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency        97468000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses                  1791                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses                  1790                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency     92487000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     92098000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses             1791                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses             1790                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.333155                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1364.601520                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           1364.601667                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           42026874                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54639.865997                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54451.396648                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51451.396648                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               42025083                       # number of overall hits
-system.cpu.dcache.overall_miss_latency       97860000                       # number of overall miss cycles
+system.cpu.dcache.overall_hits               42025084                       # number of overall hits
+system.cpu.dcache.overall_miss_latency       97468000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses                 1791                       # number of overall misses
+system.cpu.dcache.overall_misses                 1790                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency     92487000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     92098000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses            1791                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses            1790                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.replacements                     40                       # number of replacements
 system.cpu.dcache.sampled_refs                   1790                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1364.601520                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1364.601667                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 42025084                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                       16                       # number of writebacks
@@ -115,7 +115,7 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.560536                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1147.977742                       # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0           1147.977892                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          189792839                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
@@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   1506                       # number of replacements
 system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1147.977742                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1147.977892                       # Cycle average of tags in use
 system.cpu.icache.total_refs                189789788                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -150,12 +150,13 @@ system.cpu.itb.write_misses                         0                       # DT
 system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     57200000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1100                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     44000000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1100                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1092                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              3741                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
@@ -166,20 +167,11 @@ system.cpu.l2cache.ReadReq_misses                2361                       # nu
 system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631115                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency        52000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        40000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.582348                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.582524                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -188,44 +180,44 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses               4841                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1380                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      179972000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.714935                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 3461                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                   1388                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.713282                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    138440000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.714935                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            3461                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.713282                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.051044                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1                  0.000062                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          1672.604273                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             2.043764                       # Average occupied blocks per context
+system.cpu.l2cache.occ_%::1                  0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1672.604511                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.037968                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              4841                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1380                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     179972000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.714935                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                3461                       # number of overall misses
+system.cpu.l2cache.overall_hits                  1388                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.713282                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                3453                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    138440000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.714935                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           3461                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.713282                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.sampled_refs                  2368                       # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              1674.648036                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              1675.642479                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1380                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        464056124                       # number of cpu cycles simulated
+system.cpu.numCycles                        464055342                       # number of cpu cycles simulated
 system.cpu.num_insts                        186333855                       # Number of instructions executed
 system.cpu.num_refs                          42511846                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
index c1e1fc55b..8e0eaa820 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
index 705b33507..f2c1160f5 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 13:20:12
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 13:26:25
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:26:56
+M5 executing on phenom
 command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -31,4 +27,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 250960757000 because target called exit()
+122 123 124 Exiting @ tick 250960631000 because target called exit()
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 24bf72eb4..69e591ac8 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 935562                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 217504                       # Number of bytes of host memory used
-host_seconds                                   234.54                       # Real time elapsed on the host
-host_tick_rate                             1069990696                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1231791                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202836                       # Number of bytes of host memory used
+host_seconds                                   178.14                       # Real time elapsed on the host
+host_tick_rate                             1408783027                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   219431024                       # Number of instructions simulated
 sim_seconds                                  0.250961                       # Number of seconds simulated
-sim_ticks                                250960757000                       # Number of ticks simulated
+sim_ticks                                250960631000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses           56682008                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587                       # average ReadReq mshr miss latency
@@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency     17038500                       #
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses             327                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits              20514152                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency      88368000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      88242000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.000077                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                1578                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency     83634000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     83508000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000077                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses           1578                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses            77197738                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55846.719160                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55780.577428                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                77195833                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency       106388000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency       106262000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                  1905                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency    100672500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    100546500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses             1905                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.332874                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0           1363.451646                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           1363.451495                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses           77197738                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55846.719160                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55780.577428                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits               77195833                       # number of overall hits
-system.cpu.dcache.overall_miss_latency      106388000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency      106262000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                 1905                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency    100672500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    100546500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses            1905                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -69,7 +69,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                     41                       # number of replacements
 system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               1363.451646                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1363.451495                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 77195833                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        7                       # number of writebacks
@@ -106,7 +106,7 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.occ_%::0                   0.710590                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0           1455.289171                       # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0           1455.289108                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses          173494412                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
@@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                   2836                       # number of replacements
 system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1455.289171                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1455.289108                       # Cycle average of tags in use
 system.cpu.icache.total_refs                173489718                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -132,12 +132,13 @@ system.cpu.idle_fraction                            0                       # Pe
 system.cpu.l2cache.ReadExReq_accesses            1578                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency     82056000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses              1578                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     63120000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses         1578                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency     81900000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate       0.998099                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses              1575                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     63000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.998099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses         1575                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadReq_accesses              5021                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
@@ -159,46 +160,46 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses               6599                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52003.271423                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52003.273495                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                   1861                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency      246391500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.717988                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses                 4738                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                   1864                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      246235500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.717533                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                 4735                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency    189520000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.717988                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses            4738                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency    189400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.717533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses            4735                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.occ_%::0                  0.062810                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_%::1                  0.000001                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0          2058.146657                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             0.021757                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0          2058.146434                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             0.021756                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses              6599                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52003.271423                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52003.273495                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                  1861                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency     246391500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.717988                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses                4738                       # number of overall misses
+system.cpu.l2cache.overall_hits                  1864                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     246235500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.717533                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                4735                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency    189520000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.717988                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses           4738                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency    189400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.717533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses           4735                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              2058.168414                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2058.168190                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    1861                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        501921514                       # number of cpu cycles simulated
+system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
 system.cpu.num_insts                        219431024                       # Number of instructions executed
 system.cpu.num_refs                          77165306                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls             400                       # Number of system calls
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 587e758aa..c215df20a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -265,7 +265,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -285,7 +285,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -411,7 +411,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 2604d666e..0cc7c869c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:21
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:53
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 9b7657157..5844bc26e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2244323                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 293120                       # Number of bytes of host memory used
-host_seconds                                    28.14                       # Real time elapsed on the host
-host_tick_rate                            66466128576                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2584495                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 281712                       # Number of bytes of host memory used
+host_seconds                                    24.44                       # Real time elapsed on the host
+host_tick_rate                            76540345609                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -24,18 +24,18 @@ system.cpu0.dcache.ReadReq_misses::0          1683563                       # nu
 system.cpu0.dcache.ReadReq_misses::total      1683563                       # number of ReadReq misses
 system.cpu0.dcache.StoreCondReq_accesses::0       187338                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits::0        165851                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       165851                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.114696                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0        21487                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21487                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_hits::0        186635                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       186635                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003753                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0          703                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          703                       # number of StoreCondReq misses
 system.cpu0.dcache.WriteReq_accesses::0       5748261                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits::0           5400040                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5400040                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate::0     0.060578                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0          348221                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       348221                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_hits::0           5462265                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5462265                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate::0     0.049753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0          285996                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       285996                       # number of WriteReq misses
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
@@ -51,16 +51,16 @@ system.cpu0.dcache.demand_avg_miss_latency::0            0
 system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            12698146                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::0            12760371                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12698146                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12760371                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.137936                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::0       0.133711                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           2031784                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0           1969559                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2031784                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1969559                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
@@ -80,16 +80,16 @@ system.cpu0.dcache.overall_avg_miss_latency::1     no_value
 system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           12698146                       # number of overall hits
+system.cpu0.dcache.overall_hits::0           12760371                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12698146                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12760371                       # number of overall hits
 system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.137936                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::0      0.133711                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          2031784                       # number of overall misses
+system.cpu0.dcache.overall_misses::0          1969559                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2031784                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1969559                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
@@ -104,7 +104,7 @@ system.cpu0.dcache.soft_prefetch_mshr_full            0                       #
 system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
 system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  419022                       # number of writebacks
+system.cpu0.dcache.writebacks                  771740                       # number of writebacks
 system.cpu0.dtb.data_accesses                  698037                       # DTB accesses
 system.cpu0.dtb.data_acv                          251                       # DTB access violations
 system.cpu0.dtb.data_hits                    15091429                       # DTB hits
@@ -196,7 +196,7 @@ system.cpu0.icache.soft_prefetch_mshr_full            0                       #
 system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
 system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                       0                       # number of writebacks
+system.cpu0.icache.writebacks                      95                       # number of writebacks
 system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
@@ -323,18 +323,18 @@ system.cpu1.dcache.ReadReq_misses::0            41650                       # nu
 system.cpu1.dcache.ReadReq_misses::total        41650                       # number of ReadReq misses
 system.cpu1.dcache.StoreCondReq_accesses::0        16345                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_hits::0         13853                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        13853                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.152463                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0         2492                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         2492                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_hits::0         15613                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        15613                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0          732                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          732                       # number of StoreCondReq misses
 system.cpu1.dcache.WriteReq_accesses::0        733305                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits::0            703732                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        703732                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate::0     0.040328                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0           29573                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        29573                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_hits::0            707444                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        707444                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate::0     0.035266                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0           25861                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        25861                       # number of WriteReq misses
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
@@ -350,16 +350,16 @@ system.cpu1.dcache.demand_avg_miss_latency::0            0
 system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             1813047                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::0             1816759                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1813047                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1816759                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.037799                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::0       0.035829                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0             71223                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0             67511                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         71223                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         67511                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
@@ -379,16 +379,16 @@ system.cpu1.dcache.overall_avg_miss_latency::1     no_value
 system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            1813047                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            1816759                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1813047                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1816759                       # number of overall hits
 system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.037799                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::0      0.035829                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0            71223                       # number of overall misses
+system.cpu1.dcache.overall_misses::0            67511                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        71223                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        67511                       # number of overall misses
 system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
@@ -403,7 +403,7 @@ system.cpu1.dcache.soft_prefetch_mshr_full            0                       #
 system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   31228                       # number of writebacks
+system.cpu1.dcache.writebacks                   39996                       # number of writebacks
 system.cpu1.dtb.data_accesses                  323622                       # DTB accesses
 system.cpu1.dtb.data_acv                          116                       # DTB access violations
 system.cpu1.dtb.data_hits                     1914885                       # DTB hits
@@ -495,7 +495,7 @@ system.cpu1.icache.soft_prefetch_mshr_full            0                       #
 system.cpu1.icache.tagsinuse               427.126317                       # Cycle average of tags in use
 system.cpu1.icache.total_refs                 5832136                       # Total number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                       0                       # number of writebacks
+system.cpu1.icache.writebacks                      15                       # number of writebacks
 system.cpu1.idle_fraction                    0.998413                       # Percentage of idle cycles
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
@@ -680,84 +680,84 @@ system.iocache.tagsinuse                     0.435437                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               282023                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                24224                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           306247                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0                     1653                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                      139                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 1792                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0            0.994139                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.994262                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 280370                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  24085                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             304455                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0                2581832                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 142288                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2724120                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0                    1623623                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     136766                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1760389                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0              0.371135                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.038809                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   958209                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     5522                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               963731                       # number of ReadReq misses
-system.l2c.SCUpgradeReq_accesses::0             20901                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1              1879                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         22780                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_hits::0                     3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                     4                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_rate::0         0.999856                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.997871                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               20898                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                1875                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           22773                       # number of SCUpgradeReq misses
-system.l2c.UpgradeReq_accesses::0               64914                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                4352                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           69266                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0                      12                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                       3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  15                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0           0.999815                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.999311                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 64902                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  4349                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             69251                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0               450250                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           450250                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   450250                       # number of Writeback hits
-system.l2c.Writeback_hits::total               450250                       # number of Writeback hits
+system.l2c.ReadExReq_accesses::0               281898                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                23952                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           305850                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0                   164417                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    14126                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               178543                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0            0.416750                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.410237                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 117481                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   9826                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             127307                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0                2577422                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 141641                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2719063                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0                    1620505                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     137130                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1757635                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0              0.371269                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.031848                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   956917                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4511                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               961428                       # number of ReadReq misses
+system.l2c.SCUpgradeReq_accesses::0                80                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1               110                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           190                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_hits::0                    15                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                     9                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                24                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_miss_rate::0         0.812500                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.918182                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0                  65                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                 101                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             166                       # number of SCUpgradeReq misses
+system.l2c.UpgradeReq_accesses::0                2575                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                 606                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3181                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0                     134                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      39                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 173                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0           0.947961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.935644                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  2441                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   567                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3008                       # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0               811846                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           811846                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   811846                       # number of Writeback hits
+system.l2c.Writeback_hits::total               811846                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.817381                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.151871                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2863855                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  166512                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2859320                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  165593                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             3030367                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3024913                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2        no_value                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1625276                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      136905                       # number of demand (read+write) hits
+system.l2c.demand_hits::0                     1784922                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      151256                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1762181                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1936178                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.432487                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.177807                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::0               0.375753                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.086580                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                   1238579                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     29607                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                   1074398                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     14337                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1268186                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1088735                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
@@ -768,35 +768,35 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.144031                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.004095                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.343441                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                  9439.247714                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   268.394267                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 22507.731761                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2863855                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 166512                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.152888                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.004061                       # Average percentage of cache occupancy
+system.l2c.occ_%::2                          0.363646                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 10019.673951                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   266.115685                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23831.931773                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2859320                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 165593                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            3030367                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            3024913                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2       no_value                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1625276                       # number of overall hits
-system.l2c.overall_hits::1                     136905                       # number of overall hits
+system.l2c.overall_hits::0                    1784922                       # number of overall hits
+system.l2c.overall_hits::1                     151256                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                1762181                       # number of overall hits
+system.l2c.overall_hits::total                1936178                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.432487                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.177807                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::0              0.375753                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.086580                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                  1238579                       # number of overall misses
-system.l2c.overall_misses::1                    29607                       # number of overall misses
+system.l2c.overall_misses::0                  1074398                       # number of overall misses
+system.l2c.overall_misses::1                    14337                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total              1268186                       # number of overall misses
+system.l2c.overall_misses::total              1088735                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
@@ -806,13 +806,13 @@ system.l2c.overall_mshr_miss_rate::total     no_value                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                       1055565                       # number of replacements
-system.l2c.sampled_refs                       1090545                       # Sample count of references to valid blocks.
+system.l2c.replacements                       1051788                       # number of replacements
+system.l2c.sampled_refs                       1087985                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     32215.373742                       # Cycle average of tags in use
-system.l2c.total_refs                         1981936                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     34117.721410                       # Cycle average of tags in use
+system.l2c.total_refs                         2341203                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          123249                       # number of writebacks
+system.l2c.writebacks                          121798                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 95ba28054..672132c81 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -158,7 +158,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -178,7 +178,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -304,7 +304,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 88c4f9cc3..ef40fc88a 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:50
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:04:53
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index da0ed6f79..ec23533f5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2897706                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 291728                       # Number of bytes of host memory used
-host_seconds                                    20.72                       # Real time elapsed on the host
-host_tick_rate                            88290469218                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2709831                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 280300                       # Number of bytes of host memory used
+host_seconds                                    22.16                       # Real time elapsed on the host
+host_tick_rate                            82566195794                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -24,18 +24,15 @@ system.cpu.dcache.ReadReq_misses::0           1721705                       # nu
 system.cpu.dcache.ReadReq_misses::total       1721705                       # number of ReadReq misses
 system.cpu.dcache.StoreCondReq_accesses::0       199282                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0         177079                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       177079                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::0     0.111415                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0        22203                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total        22203                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_hits::0         199282                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
 system.cpu.dcache.WriteReq_accesses::0        6152574                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0            5781102                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5781102                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0      0.060377                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0           371472                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       371472                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_hits::0            5848212                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0      0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0           304362                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_refs                   6.870767                       # Average number of references to valid blocks.
@@ -51,16 +48,16 @@ system.cpu.dcache.demand_avg_miss_latency::0            0
 system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             13588884                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0             13655994                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13588884                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655994                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.133476                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0        0.129196                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            2093177                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            2026067                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2093177                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026067                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
@@ -80,16 +77,16 @@ system.cpu.dcache.overall_avg_miss_latency::1     no_value
 system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            13588884                       # number of overall hits
+system.cpu.dcache.overall_hits::0            13655994                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13588884                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655994                       # number of overall hits
 system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.133476                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.129196                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           2093177                       # number of overall misses
+system.cpu.dcache.overall_misses::0           2026067                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2093177                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026067                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
@@ -104,7 +101,7 @@ system.cpu.dcache.soft_prefetch_mshr_full            0                       # n
 system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 14038433                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   450979                       # number of writebacks
+system.cpu.dcache.writebacks                   825183                       # number of writebacks
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_hits                     16062925                       # DTB hits
@@ -196,7 +193,7 @@ system.cpu.icache.soft_prefetch_mshr_full            0                       # n
 system.cpu.icache.tagsinuse                511.215243                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 59129922                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.writebacks                      108                       # number of writebacks
 system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
@@ -393,59 +390,56 @@ system.iocache.tagsinuse                     1.225570                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               304346                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304346                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0                     1965                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 1965                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0            0.993544                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 302381                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             302381                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0                2659071                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2659071                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0                    1697753                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1697753                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0              0.361524                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   961318                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               961318                       # number of ReadReq misses
-system.l2c.SCUpgradeReq_accesses::0             22203                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         22203                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_miss_rate::0                1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               22203                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           22203                       # number of SCUpgradeReq misses
-system.l2c.UpgradeReq_accesses::0               67126                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           67126                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 67126                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             67126                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0               450979                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           450979                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   450979                       # number of Writeback hits
-system.l2c.Writeback_hits::total               450979                       # number of Writeback hits
+system.l2c.ReadExReq_accesses::0               304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0                   185383                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185383                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0            0.390673                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 118859                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             118859                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0                2659024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2659024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0                    1699395                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1699395                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0              0.360895                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   959629                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               959629                       # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0                       1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0           0.923077                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                    12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0               825291                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           825291                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   825291                       # number of Writeback hits
+system.l2c.Writeback_hits::total               825291                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.759381                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.126306                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2963417                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2963266                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2963417                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2963266                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1        no_value                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1699718                       # number of demand (read+write) hits
+system.l2c.demand_hits::0                     1884778                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1699718                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1884778                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.426433                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::0               0.363952                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                   1263699                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                   1078488                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1263699                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1078488                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
@@ -455,28 +449,28 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.141683                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.342776                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                  9285.312813                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 22464.151503                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2963417                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.155542                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.360312                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 10193.605493                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 23613.410409                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2963266                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2963417                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1       no_value                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1699718                       # number of overall hits
+system.l2c.overall_hits::0                    1884778                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1699718                       # number of overall hits
+system.l2c.overall_hits::total                1884778                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.426433                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::0              0.363952                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                  1263699                       # number of overall misses
+system.l2c.overall_misses::0                  1078488                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total              1263699                       # number of overall misses
+system.l2c.overall_misses::total              1078488                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
@@ -485,13 +479,13 @@ system.l2c.overall_mshr_miss_rate::total     no_value                       # ms
 system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                       1048986                       # number of replacements
-system.l2c.sampled_refs                       1079842                       # Sample count of references to valid blocks.
+system.l2c.replacements                       1045877                       # number of replacements
+system.l2c.sampled_refs                       1077848                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     31749.464316                       # Cycle average of tags in use
-system.l2c.total_refs                         1899854                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     33807.015903                       # Cycle average of tags in use
+system.l2c.total_refs                         2291835                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          118452                       # number of writebacks
+system.l2c.writebacks                          117189                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 425a86d16..0c4b74add 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -259,7 +259,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -279,7 +279,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -405,7 +405,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 079f41b2d..05ee0235e 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,14 +5,14 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:18
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:16:21
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 591240000
-Exiting @ tick 1967163347000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 562628000
+Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index eb5599859..c0cdf3fe8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,267 +1,267 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1510892                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289944                       # Number of bytes of host memory used
-host_seconds                                    40.42                       # Real time elapsed on the host
-host_tick_rate                            48670449492                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1372828                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 278528                       # Number of bytes of host memory used
+host_seconds                                    43.24                       # Real time elapsed on the host
+host_tick_rate                            45301058959                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    61066894                       # Number of instructions simulated
-sim_seconds                                  1.967163                       # Number of seconds simulated
-sim_ticks                                1967163347000                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses::0       150276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       150276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 11859.655689                       # average LoadLockedReq miss latency
+sim_insts                                    59355643                       # Number of instructions simulated
+sim_seconds                                  1.958647                       # Number of seconds simulated
+sim_ticks                                1958647095000                       # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses::0       193049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       193049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  8859.655689                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0       136916                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       136916                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    158445000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.088903                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        13360                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13360                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    118365000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.088903                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0       176505                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       176505                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    234949000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0        16544                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        16544                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    185317000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.085698                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        13360                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0        7279990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7279990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 26932.541490                       # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses        16544                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0        8457107                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8457107                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23932.489517                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0            6346809                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6346809                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   25132936000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0      0.128184                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0           933181                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       933181                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  22333344500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.128184                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0            7421006                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7421006                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   26570279500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0      0.122512                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0          1036101                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1036101                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23461938500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122512                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses         933181                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    883599000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0       149766                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       149766                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 42774.669320                       # average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses        1036101                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    884470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0       192084                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       192084                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  7251.219512                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 39774.669320                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0        132680                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       132680                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency    730848000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.114085                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0        17086                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        17086                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency    679590000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.114085                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  4251.219512                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0        191674                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       191674                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency      2973000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.002134                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0          410                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          410                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency      1743000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.002134                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses        17086                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0       4822937                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4822937                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 54619.723929                       # average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses          410                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0       5851669                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5851669                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 51619.723929                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0           4533446                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4533446                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency  15811918500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0     0.060024                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0          289491                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       289491                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency  14943445500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.060024                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0           5560133                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5560133                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency   9109954000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0     0.049821                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0          291536                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       291536                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8235346000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049821                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        289491                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1351640000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_misses        291536                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1242107000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  9.594836                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.970149                       # Average number of references to valid blocks.
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        12102927                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0        14308776                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12102927                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 33488.011912                       # average overall miss latency
+system.cpu0.dcache.demand_accesses::total     14308776                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 30487.972244                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            10880255                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0            12981139                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10880255                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    40944854500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.101023                       # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total        12981139                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    35680233500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0       0.092785                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           1222672                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0           1327637                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1222672                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1327637                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  37276790000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.101023                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_latency  31697284500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.092785                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1222672                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1327637                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.971951                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::0                  0.983447                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0           497.638883                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::0           503.524900                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0       12102927                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       14308776                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12102927                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 33488.011912                       # average overall miss latency
+system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 30487.972244                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           10880255                       # number of overall hits
+system.cpu0.dcache.overall_hits::0           12981139                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10880255                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   40944854500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.101023                       # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total       12981139                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   35680233500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0      0.092785                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          1222672                       # number of overall misses
+system.cpu0.dcache.overall_misses::0          1327637                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1222672                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1327637                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  37276790000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.101023                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_latency  31697284500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.092785                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1222672                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2235239000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses        1327637                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2126577000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1168722                       # number of replacements
-system.cpu0.dcache.sampled_refs               1169234                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1338438                       # number of replacements
+system.cpu0.dcache.sampled_refs               1338837                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               496.638883                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                11218608                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               502.524901                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13348404                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  339648                       # number of writebacks
-system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
-system.cpu0.dtb.data_acv                          289                       # DTB access violations
-system.cpu0.dtb.data_hits                    12394366                       # DTB hits
-system.cpu0.dtb.data_misses                      8485                       # DTB misses
+system.cpu0.dcache.writebacks                  786441                       # number of writebacks
+system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
+system.cpu0.dtb.data_acv                          344                       # DTB access violations
+system.cpu0.dtb.data_hits                    14678366                       # DTB hits
+system.cpu0.dtb.data_misses                      8256                       # DTB misses
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
-system.cpu0.dtb.read_acv                          174                       # DTB read access violations
-system.cpu0.dtb.read_hits                     7418432                       # DTB read hits
-system.cpu0.dtb.read_misses                      7687                       # DTB read misses
-system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
-system.cpu0.dtb.write_acv                         115                       # DTB write access violations
-system.cpu0.dtb.write_hits                    4975934                       # DTB write hits
-system.cpu0.dtb.write_misses                      798                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses::0       47254591                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47254591                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14914.060222                       # average ReadReq miss latency
+system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
+system.cpu0.dtb.read_acv                          210                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8633623                       # DTB read hits
+system.cpu0.dtb.read_misses                      7443                       # DTB read misses
+system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
+system.cpu0.dtb.write_acv                         134                       # DTB write access violations
+system.cpu0.dtb.write_hits                    6044743                       # DTB write hits
+system.cpu0.dtb.write_misses                      813                       # DTB write misses
+system.cpu0.icache.ReadReq_accesses::0       54081252                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     54081252                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11912.744970                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0           46572212                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       46572212                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   10177041500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0      0.014440                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           682379                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       682379                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency   8129007000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.014440                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits::0           53165471                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       53165471                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency   13429132500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate::0      0.016933                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0           915781                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       915781                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency  10681093500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.016933                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         682379                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses         915781                       # number of ReadReq MSHR misses
 system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 68.262978                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                 58.062522                       # Average number of references to valid blocks.
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0        47254591                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::0        54081252                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47254591                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 14914.060222                       # average overall miss latency
+system.cpu0.icache.demand_accesses::total     54081252                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 14664.130944                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11912.744970                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0            46572212                       # number of demand (read+write) hits
+system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits::0            53165471                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        46572212                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    10177041500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.014440                       # miss rate for demand accesses
+system.cpu0.icache.demand_hits::total        53165471                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency    13429132500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate::0       0.016933                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            682379                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::0            915781                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        682379                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        915781                       # number of demand (read+write) misses
 system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency   8129007000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0     0.014440                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_latency  10681093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate::0     0.016933                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          682379                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses          915781                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0                  0.993449                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0           508.646096                       # Average occupied blocks per context
-system.cpu0.icache.overall_accesses::0       47254591                       # number of overall (read+write) accesses
+system.cpu0.icache.occ_%::0                  0.993751                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0           508.800486                       # Average occupied blocks per context
+system.cpu0.icache.overall_accesses::0       54081252                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47254591                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 14914.060222                       # average overall miss latency
+system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 14664.130944                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11912.744970                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0           46572212                       # number of overall hits
+system.cpu0.icache.overall_hits::0           53165471                       # number of overall hits
 system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total       46572212                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   10177041500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.014440                       # miss rate for overall accesses
+system.cpu0.icache.overall_hits::total       53165471                       # number of overall hits
+system.cpu0.icache.overall_miss_latency   13429132500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate::0      0.016933                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           682379                       # number of overall misses
+system.cpu0.icache.overall_misses::0           915781                       # number of overall misses
 system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       682379                       # number of overall misses
+system.cpu0.icache.overall_misses::total       915781                       # number of overall misses
 system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency   8129007000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0     0.014440                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_latency  10681093500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate::0     0.016933                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         682379                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses         915781                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                681735                       # number of replacements
-system.cpu0.icache.sampled_refs                682247                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                915147                       # number of replacements
+system.cpu0.icache.sampled_refs                915659                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               508.646096                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                46572212                       # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           38669170000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.idle_fraction                    0.943058                       # Percentage of idle cycles
+system.cpu0.icache.tagsinuse               508.800486                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                53165471                       # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           36696092000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks                      55                       # number of writebacks
+system.cpu0.idle_fraction                    0.939737                       # Percentage of idle cycles
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_hits                           0                       # DTB hits
 system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                3572127                       # ITB accesses
-system.cpu0.itb.fetch_acv                         143                       # ITB acv
-system.cpu0.itb.fetch_hits                    3568286                       # ITB hits
-system.cpu0.itb.fetch_misses                     3841                       # ITB misses
+system.cpu0.itb.fetch_accesses                3856928                       # ITB accesses
+system.cpu0.itb.fetch_acv                         184                       # ITB acv
+system.cpu0.itb.fetch_hits                    3853057                       # ITB hits
+system.cpu0.itb.fetch_misses                     3871                       # ITB misses
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -271,350 +271,349 @@ system.cpu0.itb.write_acv                           0                       # DT
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  540      0.37%      0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.37% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.37% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 2975      2.03%      2.41% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      44      0.03%      2.44% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.44% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               131234     89.72%     92.16% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6694      4.58%     96.73% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.73% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.74% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.00%     96.74% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.74% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4260      2.91%     99.65% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 356      0.24%     99.90% # number of callpals executed
-system.cpu0.kern.callpal::imb                     149      0.10%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                146277                       # number of callpals executed
+system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               172198     91.50%     93.64% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6678      3.55%     97.19% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4751      2.52%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
+system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                188203                       # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    161605                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6835                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0                   55380     40.11%     40.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.21% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1982      1.44%     41.64% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    455      0.33%     41.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  80115     58.03%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              138063                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    54908     49.06%     49.06% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.12%     49.17% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1982      1.77%     50.94% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     455      0.41%     51.35% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   54453     48.65%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               111929                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1909262510000     97.06%     97.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               87868000      0.00%     97.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              573921000      0.03%     97.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              337802000      0.02%     97.11% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            56900501000      2.89%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1967162602000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.991477                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.hwrei                    202972                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6380                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count::0                   72739     40.62%     40.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1975      1.10%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 104211     58.20%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              179062                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    71372     49.27%     49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1975      1.36%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   71366     49.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               144850                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1899667899000     97.02%     97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               79058000      0.00%     97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              565985500      0.03%     97.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                4729500      0.00%     97.05% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            57694185000      2.95%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1958011857000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981207                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.679685                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1231                      
-system.cpu0.kern.mode_good::user                 1232                      
+system.cpu0.kern.ipl_used::31                0.684822                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel               1283                      
+system.cpu0.kern.mode_good::user                 1283                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch::kernel             6788                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1232                       # number of protection mode switches
+system.cpu0.kern.mode_switch::kernel             7302                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.181349                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1963346065000     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3816535000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    2976                       # number of times the context was actually changed
-system.cpu0.kern.syscall::2                         6      2.68%      2.68% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.48%     11.16% # number of syscalls executed
-system.cpu0.kern.syscall::4                         3      1.34%     12.50% # number of syscalls executed
-system.cpu0.kern.syscall::6                        30     13.39%     25.89% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.45%     26.34% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.45%     26.79% # number of syscalls executed
-system.cpu0.kern.syscall::17                       10      4.46%     31.25% # number of syscalls executed
-system.cpu0.kern.syscall::19                        6      2.68%     33.93% # number of syscalls executed
-system.cpu0.kern.syscall::20                        4      1.79%     35.71% # number of syscalls executed
-system.cpu0.kern.syscall::23                        2      0.89%     36.61% # number of syscalls executed
-system.cpu0.kern.syscall::24                        4      1.79%     38.39% # number of syscalls executed
-system.cpu0.kern.syscall::33                        8      3.57%     41.96% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.89%     42.86% # number of syscalls executed
-system.cpu0.kern.syscall::45                       39     17.41%     60.27% # number of syscalls executed
-system.cpu0.kern.syscall::47                        4      1.79%     62.05% # number of syscalls executed
-system.cpu0.kern.syscall::48                        7      3.12%     65.18% # number of syscalls executed
-system.cpu0.kern.syscall::54                        9      4.02%     69.20% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.45%     69.64% # number of syscalls executed
-system.cpu0.kern.syscall::59                        5      2.23%     71.88% # number of syscalls executed
-system.cpu0.kern.syscall::71                       32     14.29%     86.16% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.34%     87.50% # number of syscalls executed
-system.cpu0.kern.syscall::74                        9      4.02%     91.52% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.45%     91.96% # number of syscalls executed
-system.cpu0.kern.syscall::90                        2      0.89%     92.86% # number of syscalls executed
-system.cpu0.kern.syscall::92                        7      3.12%     95.98% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.89%     96.87% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.89%     97.77% # number of syscalls executed
-system.cpu0.kern.syscall::132                       2      0.89%     98.66% # number of syscalls executed
-system.cpu0.kern.syscall::144                       1      0.45%     99.11% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   224                       # number of syscalls executed
-system.cpu0.not_idle_fraction                0.056942                       # Percentage of non-idle cycles
-system.cpu0.numCycles                      3934326694                       # number of cpu cycles simulated
-system.cpu0.num_insts                        47245816                       # Number of instructions executed
-system.cpu0.num_refs                         12627213                       # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses::0        61432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        61432                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10283.624203                       # average LoadLockedReq miss latency
+system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
+system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
+system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
+system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
+system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
+system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
+system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
+system.cpu0.num_insts                        54072652                       # Number of instructions executed
+system.cpu0.num_refs                         14919880                       # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7283.624203                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0        51863                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        51863                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     98404000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.155766                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0         9569                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9569                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     69697000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.155766                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0        11784                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        11784                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     13079000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0          982                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total          982                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10133000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.076923                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         9569                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0        2468175                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2468175                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 13829.556740                       # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses          982                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0        1040274                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1040274                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10829.528932                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0            2342312                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2342312                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency    1740629500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0      0.050994                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0           125863                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       125863                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1363037000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.050994                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0            1003161                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1003161                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency     533263000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0      0.035676                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0            37113                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total        37113                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency    421922000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035676                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses         125863                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     12526000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0        60921                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        60921                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35881.530265                       # average StoreCondReq miss latency
+system.cpu1.dcache.ReadReq_mshr_misses          37113                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     11413500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses::0        12031                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        12031                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32881.530265                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0         47407                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        47407                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency    484903000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.221828                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0        13514                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        13514                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency    444361000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.221828                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9704.950495                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0         11526                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        11526                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency      6416000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.041975                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0          505                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          505                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency      4901000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.041975                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses        13514                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0       1805806                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1805806                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 52324.342254                       # average WriteReq miss latency
+system.cpu1.dcache.StoreCondReq_mshr_misses          505                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses::0        637320                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       637320                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 49324.342254                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0           1713103                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1713103                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency   4850623500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0     0.051336                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0           92703                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        92703                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency   4572514500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.051336                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0            616899                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        616899                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency    556796000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0     0.032042                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0           20421                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        20421                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency    495533000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.032042                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         92703                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    413889500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_misses         20421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    298050500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 23.182705                       # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs                 30.762530                       # Average number of references to valid blocks.
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         4273981                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0         1677594                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4273981                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 30156.808470                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::total      1677594                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 27156.792456                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             4055415                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0             1620060                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         4055415                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     6591253000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.051139                       # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total         1620060                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     1090059000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0       0.034296                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0            218566                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0             57534                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        218566                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         57534                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   5935551500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.051139                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_latency    917455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.034296                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses          218566                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses           57534                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.916301                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0           469.145893                       # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0        4273981                       # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0                  0.760784                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0           389.521271                       # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0        1677594                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4273981                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 30156.808470                       # average overall miss latency
+system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 27156.792456                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            4055415                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            1620060                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        4055415                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    6591253000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.051139                       # miss rate for overall accesses
+system.cpu1.dcache.overall_hits::total        1620060                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    1090059000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate::0      0.034296                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0           218566                       # number of overall misses
+system.cpu1.dcache.overall_misses::0            57534                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       218566                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        57534                       # number of overall misses
 system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   5935551500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.051139                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_latency    917455000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.034296                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses         218566                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    426415500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses          57534                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    309464000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                180512                       # number of replacements
-system.cpu1.dcache.sampled_refs                180909                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                 52960                       # number of replacements
+system.cpu1.dcache.sampled_refs                 53472                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               469.145893                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 4193960                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1949703501000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   96724                       # number of writebacks
-system.cpu1.dtb.data_accesses                  302878                       # DTB accesses
-system.cpu1.dtb.data_acv                           84                       # DTB access violations
-system.cpu1.dtb.data_hits                     4382020                       # DTB hits
-system.cpu1.dtb.data_misses                      3106                       # DTB misses
+system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1644934                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1942411783000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                   29784                       # number of writebacks
+system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
+system.cpu1.dtb.data_acv                           29                       # DTB access violations
+system.cpu1.dtb.data_hits                     1701325                       # DTB hits
+system.cpu1.dtb.data_misses                      3333                       # DTB misses
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
-system.cpu1.dtb.read_acv                           36                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2517470                       # DTB read hits
-system.cpu1.dtb.read_misses                      2750                       # DTB read misses
-system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
-system.cpu1.dtb.write_acv                          48                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1864550                       # DTB write hits
-system.cpu1.dtb.write_misses                      356                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses::0       13824268                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13824268                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14182.361205                       # average ReadReq miss latency
+system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
+system.cpu1.dtb.read_acv                            0                       # DTB read access violations
+system.cpu1.dtb.read_hits                     1050117                       # DTB read hits
+system.cpu1.dtb.read_misses                      2992                       # DTB read misses
+system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
+system.cpu1.dtb.write_acv                          29                       # DTB write access violations
+system.cpu1.dtb.write_hits                     651208                       # DTB write hits
+system.cpu1.dtb.write_misses                      341                       # DTB write misses
+system.cpu1.icache.ReadReq_accesses::0        5286354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      5286354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11182.239180                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0           13488270                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       13488270                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    4765245000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0      0.024305                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0           335998                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       335998                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   3757210000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.024305                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0            5199349                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5199349                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    1260607500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate::0      0.016458                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0            87005                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total        87005                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency    999558500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.016458                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses         335998                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses          87005                       # number of ReadReq MSHR misses
 system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                 40.147245                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 59.783935                       # Average number of references to valid blocks.
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0        13824268                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::0         5286354                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13824268                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14182.361205                       # average overall miss latency
+system.cpu1.icache.demand_accesses::total      5286354                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14488.908683                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11182.239180                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0            13488270                       # number of demand (read+write) hits
+system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits::0             5199349                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        13488270                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     4765245000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.024305                       # miss rate for demand accesses
+system.cpu1.icache.demand_hits::total         5199349                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     1260607500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate::0       0.016458                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0            335998                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::0             87005                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        335998                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total         87005                       # number of demand (read+write) misses
 system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   3757210000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0     0.024305                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_latency    999558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate::0     0.016458                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses          335998                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses           87005                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0                  0.872600                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0           446.771254                       # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0       13824268                       # number of overall (read+write) accesses
+system.cpu1.icache.occ_%::0                  0.819937                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0           419.807616                       # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0        5286354                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13824268                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14182.361205                       # average overall miss latency
+system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14488.908683                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11182.239180                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0           13488270                       # number of overall hits
+system.cpu1.icache.overall_hits::0            5199349                       # number of overall hits
 system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total       13488270                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    4765245000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.024305                       # miss rate for overall accesses
+system.cpu1.icache.overall_hits::total        5199349                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    1260607500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate::0      0.016458                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0           335998                       # number of overall misses
+system.cpu1.icache.overall_misses::0            87005                       # number of overall misses
 system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       335998                       # number of overall misses
+system.cpu1.icache.overall_misses::total        87005                       # number of overall misses
 system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   3757210000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0     0.024305                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_latency    999558500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate::0     0.016458                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses         335998                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses          87005                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                335458                       # number of replacements
-system.cpu1.icache.sampled_refs                335970                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                 86457                       # number of replacements
+system.cpu1.icache.sampled_refs                 86969                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               446.771254                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                13488270                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1962800602000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.idle_fraction                    0.984741                       # Percentage of idle cycles
+system.cpu1.icache.tagsinuse               419.807616                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 5199349                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1942711132000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                      14                       # number of writebacks
+system.cpu1.idle_fraction                    0.995135                       # Percentage of idle cycles
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_hits                           0                       # DTB hits
 system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                1913285                       # ITB accesses
-system.cpu1.itb.fetch_acv                          41                       # ITB acv
-system.cpu1.itb.fetch_hits                    1912039                       # ITB hits
-system.cpu1.itb.fetch_misses                     1246                       # ITB misses
+system.cpu1.itb.fetch_accesses                1494654                       # ITB accesses
+system.cpu1.itb.fetch_acv                           0                       # ITB acv
+system.cpu1.itb.fetch_hits                    1493438                       # ITB hits
+system.cpu1.itb.fetch_misses                     1216                       # ITB misses
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -624,85 +623,76 @@ system.cpu1.itb.write_acv                           0                       # DT
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  455      0.60%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2159      2.85%      3.46% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      10      0.01%      3.47% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.48% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                66683     88.18%     91.66% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2168      2.87%     94.53% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.53% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     94.53% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.00%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.54% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3936      5.20%     99.74% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 161      0.21%     99.96% # number of callpals executed
-system.cpu1.kern.callpal::imb                      31      0.04%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                24309     82.25%     83.46% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
+system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 75623                       # number of callpals executed
+system.cpu1.kern.callpal::total                 29554                       # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     82618                       # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce                    2771                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count::0                   28203     38.56%     38.56% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1977      2.70%     41.27% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    540      0.74%     42.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  42416     58.00%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               73136                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    27298     48.25%     48.25% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1977      3.49%     51.75% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     540      0.95%     52.70% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   26759     47.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                56574                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1915291540500     97.38%     97.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              515904000      0.03%     97.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              422495500      0.02%     97.43% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            50571037000      2.57%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1966800977000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.967911                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei                     36191                       # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce                    2318                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count::0                    9289     32.15%     32.15% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                     88      0.30%     39.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  17551     60.74%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               28897                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                     9279     45.20%     45.20% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                      88      0.43%     55.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                    9191     44.78%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                20527                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1917878582000     97.92%     97.92% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              507844000      0.03%     97.94% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               54239000      0.00%     97.95% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            40205672000      2.05%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1958646337000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.630870                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel                981                      
-system.cpu1.kern.mode_good::user                  517                      
-system.cpu1.kern.mode_good::idle                  464                      
-system.cpu1.kern.mode_switch::kernel             2246                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                517                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2954                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel     0.436776                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used::31                0.523674                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good::kernel                477                      
+system.cpu1.kern.mode_good::user                  464                      
+system.cpu1.kern.mode_good::idle                   13                      
+system.cpu1.kern.mode_switch::kernel              804                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2064                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good::kernel     0.593284                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.157075                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.593852                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       23054472000      1.17%      1.17% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1704524000      0.09%      1.26% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1941246244000     98.74%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2160                       # number of times the context was actually changed
-system.cpu1.kern.syscall::2                         2      1.96%      1.96% # number of syscalls executed
-system.cpu1.kern.syscall::3                        11     10.78%     12.75% # number of syscalls executed
-system.cpu1.kern.syscall::4                         1      0.98%     13.73% # number of syscalls executed
-system.cpu1.kern.syscall::6                        12     11.76%     25.49% # number of syscalls executed
-system.cpu1.kern.syscall::17                        5      4.90%     30.39% # number of syscalls executed
-system.cpu1.kern.syscall::19                        4      3.92%     34.31% # number of syscalls executed
-system.cpu1.kern.syscall::20                        2      1.96%     36.27% # number of syscalls executed
-system.cpu1.kern.syscall::23                        2      1.96%     38.24% # number of syscalls executed
-system.cpu1.kern.syscall::24                        2      1.96%     40.20% # number of syscalls executed
-system.cpu1.kern.syscall::33                        3      2.94%     43.14% # number of syscalls executed
-system.cpu1.kern.syscall::45                       15     14.71%     57.84% # number of syscalls executed
-system.cpu1.kern.syscall::47                        2      1.96%     59.80% # number of syscalls executed
-system.cpu1.kern.syscall::48                        3      2.94%     62.75% # number of syscalls executed
-system.cpu1.kern.syscall::54                        1      0.98%     63.73% # number of syscalls executed
-system.cpu1.kern.syscall::59                        2      1.96%     65.69% # number of syscalls executed
-system.cpu1.kern.syscall::71                       22     21.57%     87.25% # number of syscalls executed
-system.cpu1.kern.syscall::74                        7      6.86%     94.12% # number of syscalls executed
-system.cpu1.kern.syscall::90                        1      0.98%     95.10% # number of syscalls executed
-system.cpu1.kern.syscall::92                        2      1.96%     97.06% # number of syscalls executed
-system.cpu1.kern.syscall::132                       2      1.96%     99.02% # number of syscalls executed
-system.cpu1.kern.syscall::144                       1      0.98%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   102                       # number of syscalls executed
-system.cpu1.not_idle_fraction                0.015259                       # Percentage of non-idle cycles
-system.cpu1.numCycles                      3933602014                       # number of cpu cycles simulated
-system.cpu1.num_insts                        13821078                       # Number of instructions executed
-system.cpu1.num_refs                          4410345                       # Number of memory references
+system.cpu1.kern.mode_switch_good::idle      0.006298                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.599582                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        3571416000      0.18%      0.18% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1745054000      0.09%      0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1953329865000     99.73%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
+system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
+system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
+system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
+system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
+system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
+system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
+system.cpu1.num_insts                         5282991                       # Number of instructions executed
+system.cpu1.num_refs                          1711037                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -733,37 +723,37 @@ system.iocache.ReadReq_mshr_misses                174                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137872.733106                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137701.766606                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85869.242491                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5728887806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5721783806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3568038764                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3560928000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6165.774548                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64487836                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137778.382879                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137608.129320                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85774.906821                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5748940804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741836804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -771,7 +761,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3579043762                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571932998                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -779,20 +769,20 @@ system.iocache.demand_mshr_misses               41726                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.036248                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 0.579966                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.035233                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 0.563721                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137778.382879                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137608.129320                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85774.906821                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5748940804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741836804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -800,7 +790,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41726                       # number of overall misses
 system.iocache.overall_misses::total            41726                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3579043762                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571932998                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -810,195 +800,196 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41694                       # number of replacements
 system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     0.579966                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1759378217000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1751545158000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               236787                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                61172                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           297959                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 65502.824330                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 252326.309748                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               287834                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                18765                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           306599                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 54743.487656                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.055004                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                     1864                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                      187                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 2051                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency         15388120000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.992128                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.996943                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 234923                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  60985                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             295908                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    11837224000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       1.249680                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       4.837311                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   170288                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    12569                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               182857                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6434878000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.408381                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.330189                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 117546                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   6196                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             123742                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4949974000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.429908                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       6.594298                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               295908                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                1614705                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 454179                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2068884                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52561.218952                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   5017624.332810                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               123742                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                1962222                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 121144                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2083366                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52352.135047                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   8117583.205325                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.414894                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1310657                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     450994                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1761651                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           15981133500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.188299                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.007013                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   304048                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     3185                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               307233                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                       12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12293883000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.190264                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.676432                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0                    1659395                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     119191                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1778586                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           15853640000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.154329                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.016121                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   302827                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     1953                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               304780                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                       11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency      12195855000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.155318                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         2.515758                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 307221                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    802535000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0             12669                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1              8188                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         20857                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 78597.820938                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 121582.804104                       # average SCUpgradeReq miss latency
+system.l2c.ReadReq_mshr_misses                 304769                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    802314500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_accesses::0                33                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1                93                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           126                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1  5621.621622                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.028004                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_hits::0                     3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency        995520000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0         0.999763                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1                1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               12666                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                8188                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           20854                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency    834244000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.646065                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     2.546898                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_hits::0                    18                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                    19                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                37                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_miss_latency           416000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_rate::0         0.454545                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.795699                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0                  15                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                  74                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total              89                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_mshr_miss_latency      3560000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_rate::0     2.696970                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1     0.956989                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses             20854                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0               46404                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1               25015                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           71419                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 74757.458826                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 138647.409244                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_mshr_misses                89                       # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0                2625                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                 548                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3173                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0  1232.776192                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  6109.090909                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40008.977591                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                      16                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                       3                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  19                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency         3467849000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.999655                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.999880                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 46388                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                 25012                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             71400                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    2856641000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.538660                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      2.854287                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                     172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      53                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 225                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency            3024000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.934476                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.903285                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  2453                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   495                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2948                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency     117981000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.123048                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      5.379562                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               71400                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                2948                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1594965500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               436372                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           436372                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   436372                       # number of Writeback hits
-system.l2c.Writeback_hits::total               436372                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1391411500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               816294                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           816294                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   816294                       # number of Writeback hits
+system.l2c.Writeback_hits::total               816294                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.549954                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.543761                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 1851492                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  515351                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2250056                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  139909                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2366843                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    58202.117554                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    488846.088515                       # average overall miss latency
+system.l2c.demand_accesses::total             2389965                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    53020.812469                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    2735123.082587                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40009.860245                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1312521                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      451181                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40012.576107                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1829683                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      131760                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1763702                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31369253500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.291101                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.124517                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 1961443                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22288518000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.186828                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.058245                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    538971                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     64170                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    420373                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                      8149                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                603141                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                        12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24131107000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.325753                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.170327                       # mshr miss rate for demand accesses
+system.l2c.demand_misses::total                428522                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency       17145829000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.190445                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          3.062784                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  603129                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  428511                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.162138                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.003912                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.340573                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 10625.898715                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   256.359763                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 22319.780586                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                1851492                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 515351                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.165831                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.003052                       # Average percentage of cache occupancy
+system.l2c.occ_%::2                          0.357359                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 10867.929163                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   199.983935                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23419.887612                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2250056                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 139909                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2366843                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   58202.117554                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   488846.088515                       # average overall miss latency
+system.l2c.overall_accesses::total            2389965                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   53020.812469                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   2735123.082587                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.860245                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40012.576107                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1312521                       # number of overall hits
-system.l2c.overall_hits::1                     451181                       # number of overall hits
+system.l2c.overall_hits::0                    1829683                       # number of overall hits
+system.l2c.overall_hits::1                     131760                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                1763702                       # number of overall hits
-system.l2c.overall_miss_latency           31369253500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.291101                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.124517                       # miss rate for overall accesses
+system.l2c.overall_hits::total                1961443                       # number of overall hits
+system.l2c.overall_miss_latency           22288518000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.186828                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.058245                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   538971                       # number of overall misses
-system.l2c.overall_misses::1                    64170                       # number of overall misses
+system.l2c.overall_misses::0                   420373                       # number of overall misses
+system.l2c.overall_misses::1                     8149                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               603141                       # number of overall misses
-system.l2c.overall_mshr_hits                       12                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24131107000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.325753                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.170327                       # mshr miss rate for overall accesses
+system.l2c.overall_misses::total               428522                       # number of overall misses
+system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency      17145829000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.190445                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         3.062784                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 603129                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2397500500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 428511                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2193726000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        398396                       # number of replacements
-system.l2c.sampled_refs                        431420                       # Sample count of references to valid blocks.
+system.l2c.replacements                        393576                       # number of replacements
+system.l2c.sampled_refs                        427769                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     33202.039064                       # Cycle average of tags in use
-system.l2c.total_refs                         1962941                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                   10911264000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          122806                       # number of writebacks
+system.l2c.tagsinuse                     34487.800710                       # Cycle average of tags in use
+system.l2c.total_refs                         2371449                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                   10882116000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          119935                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index 7399f4d84..aa80e0b5e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
unix_boot_mem ends at FFFFFC0000078000 
 
k_argc = 0 
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
-
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
+
CallbackFixup 0 18000, t7=FFFFFC000070C000
 
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 14a4f1725..88a03573e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -8,12 +8,12 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/home/stever/m5/m5_system_2.0b3/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -155,7 +155,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -175,7 +175,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -301,7 +301,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index 8049df732..76f93cc23 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 12:51:14
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 12:51:16
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:50
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:15:41
+M5 executing on phenom
 command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1927951878000 because m5_exit instruction encountered
+Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 3b140faa7..f831d68d8 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,265 +1,252 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1563603                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 288804                       # Number of bytes of host memory used
-host_seconds                                    35.93                       # Real time elapsed on the host
-host_tick_rate                            53658174093                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1445061                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 277124                       # Number of bytes of host memory used
+host_seconds                                    38.85                       # Real time elapsed on the host
+host_tick_rate                            49309117653                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56180319                       # Number of instructions simulated
-sim_seconds                                  1.927952                       # Number of seconds simulated
-sim_ticks                                1927951878000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0       200373                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200373                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14335.708080                       # average LoadLockedReq miss latency
+sim_insts                                    56137087                       # Number of instructions simulated
+sim_seconds                                  1.915549                       # Number of seconds simulated
+sim_ticks                                1915548867000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0       200226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11335.708080                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        183108                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183108                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    247506000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.086164                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        17265                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17265                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    195711000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.086164                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0        183025                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183025                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    245980000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0        17201                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17201                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    194377000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.085908                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17265                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         8883579                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8883579                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25418.459915                       # average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses        17201                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses::0         8876646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8876646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22418.417380                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             7813872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7813872                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    27190304500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.120414                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1069707                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069707                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  23981138000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.120414                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0             7807536                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807536                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    27121920500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.120441                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0           1069110                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069110                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  23914545000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.120441                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1069707                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses         1069110                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency    862763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       199352                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199352                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.626718                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.626718                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0         177090                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       177090                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency   1246775000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate::0     0.111672                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0        22262                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total        22262                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency   1179989000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.111672                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses        22262                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0        6156793                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6156793                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 55757.232436                       # average WriteReq miss latency
+system.cpu.dcache.StoreCondReq_accesses::0       199203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0         199203                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199203                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0        6152889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52757.232436                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            5786171                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5786171                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   20664857000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.060197                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0           370622                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       370622                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  19552991000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.060197                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0            5848554                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848554                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    9228484000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.049462                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0           304335                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   8315479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.049462                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         370622                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1200971000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_misses         304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1199607500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  10.097149                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.094968                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15040372                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0         15029535                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15040372                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 33225.160016                       # average overall miss latency
+system.cpu.dcache.demand_accesses::total     15029535                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26466.589124                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30225.128426                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             13600043                       # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             13656090                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13600043                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     47855161500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.095764                       # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total         13656090                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     36350404500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.091383                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            1440329                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            1373445                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1440329                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373445                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  43534129000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.095764                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency  32230024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.091383                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1440329                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1373445                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999969                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            511.984152                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0        15040372                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0            511.984023                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15040372                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 33225.160016                       # average overall miss latency
+system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26466.589124                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30225.128426                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            13600043                       # number of overall hits
+system.cpu.dcache.overall_hits::0            13656090                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13600043                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    47855161500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.095764                       # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total        13656090                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    36350404500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.091383                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           1440329                       # number of overall misses
+system.cpu.dcache.overall_misses::0           1373445                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1440329                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373445                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  43534129000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.095764                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_latency  32230024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.091383                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1440329                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2063734000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses         1373445                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2062370500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1390845                       # number of replacements
-system.cpu.dcache.sampled_refs                1391357                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1390115                       # number of replacements
+system.cpu.dcache.sampled_refs                1390627                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.984152                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14048739                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038335                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               84029000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   452168                       # number of writebacks
-system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
+system.cpu.dcache.writebacks                   826586                       # number of writebacks
+system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_hits                     15421062                       # DTB hits
-system.cpu.dtb.data_misses                      11466                       # DTB misses
+system.cpu.dtb.data_hits                     15409957                       # DTB hits
+system.cpu.dtb.data_misses                      11452                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
+system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      9064565                       # DTB read hits
-system.cpu.dtb.read_misses                      10324                       # DTB read misses
-system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
+system.cpu.dtb.read_hits                      9057511                       # DTB read hits
+system.cpu.dtb.read_misses                      10312                       # DTB read misses
+system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6356497                       # DTB write hits
-system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::0        56192153                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56192153                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14699.293599                       # average ReadReq miss latency
+system.cpu.dtb.write_hits                     6352446                       # DTB write hits
+system.cpu.dtb.write_misses                      1140                       # DTB write misses
+system.cpu.icache.ReadReq_accesses::0        56148907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56148907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.559265                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0            55261378                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55261378                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    13681735000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.016564                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0            930775                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        930775                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency  10888726500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.016564                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0            55220553                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55220553                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    13616370500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.016534                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0            928354                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        928354                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency  10830625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.016534                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          930775                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses          928354                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  59.381568                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  59.492469                       # Average number of references to valid blocks.
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0         56192153                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0         56148907                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56192153                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14699.293599                       # average overall miss latency
+system.cpu.icache.demand_accesses::total     56148907                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14667.218001                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11698.559265                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0             55261378                       # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0             55220553                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55261378                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     13681735000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.016564                       # miss rate for demand accesses
+system.cpu.icache.demand_hits::total         55220553                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     13616370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.016534                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0             930775                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0             928354                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         930775                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         928354                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  10888726500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.016564                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_latency  10830625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.016534                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           930775                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses           928354                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.993310                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            508.574724                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0        56192153                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.993597                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            508.721464                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0        56148907                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56192153                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14699.293599                       # average overall miss latency
+system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14667.218001                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11698.559265                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0            55261378                       # number of overall hits
+system.cpu.icache.overall_hits::0            55220553                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total        55261378                       # number of overall hits
-system.cpu.icache.overall_miss_latency    13681735000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.016564                       # miss rate for overall accesses
+system.cpu.icache.overall_hits::total        55220553                       # number of overall hits
+system.cpu.icache.overall_miss_latency    13616370500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.016534                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0            930775                       # number of overall misses
+system.cpu.icache.overall_misses::0            928354                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        930775                       # number of overall misses
+system.cpu.icache.overall_misses::total        928354                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  10888726500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.016564                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_latency  10830625500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.016534                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          930775                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses          928354                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 930104                       # number of replacements
-system.cpu.icache.sampled_refs                 930615                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 927683                       # number of replacements
+system.cpu.icache.sampled_refs                 928194                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                508.574724                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55261378                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle            38310365000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                     0.930310                       # Percentage of idle cycles
+system.cpu.icache.tagsinuse                508.721464                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55220553                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle            36307428000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                       85                       # number of writebacks
+system.cpu.idle_fraction                     0.936531                       # Percentage of idle cycles
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 4982567                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4978517                       # ITB accesses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_hits                     4977557                       # ITB hits
-system.cpu.itb.fetch_misses                      5010                       # ITB misses
+system.cpu.itb.fetch_hits                     4973520                       # ITB hits
+system.cpu.itb.fetch_misses                      4997                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -272,55 +259,55 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.16%      2.16% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4173      2.16%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                176202     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6843      3.54%     96.95% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175927     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rti                     5167      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 193169                       # number of callpals executed
+system.cpu.kern.callpal::total                 192868                       # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     212271                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6373                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74979     40.87%     40.87% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1942      1.06%     42.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106391     58.00%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183443                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73612     49.31%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.39% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1942      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73612     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149297                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1865248449500     96.75%     96.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                84324500      0.00%     96.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               564095000      0.03%     96.78% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             62054251000      3.22%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1927951120000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981768                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei                     211932                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count::0                    74887     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1931      1.05%     42.02% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106197     57.98%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183146                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73520     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1931      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73520     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149102                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1857816228500     96.99%     96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                79988500      0.00%     96.99% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               554693000      0.03%     97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             57097199000      2.98%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1915548109000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981746                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.691901                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel                1914                      
-system.cpu.kern.mode_good::user                  1744                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch::kernel              5914                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1744                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.323639                       # fraction of useful protection mode switches
+system.cpu.kern.ipl_used::31                 0.692298                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good::kernel                1906                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   168                      
+system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2092                       # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.322887                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.404746                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        47869140000      2.48%      2.48% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5515150000      0.29%      2.77% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1874566828000     97.23%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.403193                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        45253274000      2.36%      2.36% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5124228000      0.27%      2.63% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1865170605000     97.37%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4174                       # number of times the context was actually changed
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -352,10 +339,10 @@ system.cpu.kern.syscall::132                        4      1.23%     98.77% # nu
 system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.not_idle_fraction                 0.069690                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3855903756                       # number of cpu cycles simulated
-system.cpu.num_insts                         56180319                       # Number of instructions executed
-system.cpu.num_refs                          15669216                       # Number of memory references
+system.cpu.not_idle_fraction                 0.063469                       # Percentage of non-idle cycles
+system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
+system.cpu.num_insts                         56137087                       # Number of instructions executed
+system.cpu.num_refs                          15658046                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -371,14 +358,14 @@ system.disk2.dma_write_txs                          1                       # Nu
 system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115254.323699                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115265.884393                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency          19938998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          19940998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency     10942998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     10944998                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
@@ -386,37 +373,37 @@ system.iocache.ReadReq_mshr_misses                173                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137846.765643                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137714.208847                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85843.300347                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5727808806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5722300806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3566960816                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561447990                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6165.192131                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6166.863307                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs                10472                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64561892                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137753.092966                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137621.133709                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85749.642037                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5747747804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5742241804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -424,7 +411,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3577903814                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572392988                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -432,20 +419,20 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.084569                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 1.353112                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.083770                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 1.340325                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137753.092966                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137621.133709                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85749.642037                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5747747804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5742241804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -453,7 +440,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3577903814                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572392988                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -463,153 +450,140 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.353112                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1760339542000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1750545944000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               304386                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304386                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52003.580327                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               304172                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304172                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52003.930884                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.580327                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                     2179                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 2179                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency         15715846000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.992841                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 302207                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             302207                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    12089362000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.992841                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   185878                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185878                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6151753000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.388905                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 118294                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             118294                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4732225000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.388905                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               302207                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                2017728                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2017728                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52016.477812                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               118294                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                2014599                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2014599                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52016.540189                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.459857                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1711407                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1711407                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           15933739500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.151815                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   306321                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               306321                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency      12257882000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.151815                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0                    1710461                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1710461                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           15820206500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.150967                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   304138                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               304138                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency      12170545000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.150967                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 306321                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses                 304138                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_uncacheable_latency    772673000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0             22262                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         22262                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.626718                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.626718                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_miss_latency       1157727000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0                1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0               22262                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           22262                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency    890583000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses             22262                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0               66236                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           66236                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 52000.030195                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40007.095839                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         3444274000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                 66236                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             66236                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    2649910000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0             1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                       6                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency             248000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.538462                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                     7                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency        320000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.538462                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               66236                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                   7                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1085051000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               452168                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           452168                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   452168                       # number of Writeback hits
-system.l2c.Writeback_hits::total               452168                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1083819500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               826671                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           826671                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   826671                       # number of Writeback hits
+system.l2c.Writeback_hits::total               826671                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.517115                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.479364                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2322114                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2318771                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2322114                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52010.072667                       # average overall miss latency
+system.l2c.demand_accesses::total             2318771                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52013.009194                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40010.063629                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1713586                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40012.996175                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1896339                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1713586                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31649585500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.262058                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 1896339                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            21971959500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.182179                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    608528                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    422432                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                608528                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                422432                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24347244000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.262058                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency       16902770000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.182179                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  608528                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  422432                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.156745                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.334961                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 10272.459916                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 21951.974033                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2322114                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.171530                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.352641                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 11241.373247                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 23110.665097                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2318771                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2322114                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52010.072667                       # average overall miss latency
+system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52013.009194                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40010.063629                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40012.996175                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1713586                       # number of overall hits
+system.l2c.overall_hits::0                    1896339                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1713586                       # number of overall hits
-system.l2c.overall_miss_latency           31649585500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.262058                       # miss rate for overall accesses
+system.l2c.overall_hits::total                1896339                       # number of overall hits
+system.l2c.overall_miss_latency           21971959500                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.182179                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   608528                       # number of overall misses
+system.l2c.overall_misses::0                   422432                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               608528                       # number of overall misses
+system.l2c.overall_misses::total               422432                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24347244000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.262058                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency      16902770000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.182179                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 608528                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1857724000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 422432                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1856492500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        393234                       # number of replacements
-system.l2c.sampled_refs                        424575                       # Sample count of references to valid blocks.
+system.l2c.replacements                        389289                       # number of replacements
+system.l2c.sampled_refs                        421794                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     32224.433949                       # Cycle average of tags in use
-system.l2c.total_refs                         1917854                       # Total number of references to valid blocks.
-system.l2c.warmup_cycle                    6967096000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          118566                       # number of writebacks
+system.l2c.tagsinuse                     34352.038344                       # Cycle average of tags in use
+system.l2c.total_refs                         2311163                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                    6937912000                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                          116650                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
index ac8ae900f..78382173c 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu4: completed 10000 read accesses @26562477
-system.cpu0: completed 10000 read accesses @26652602
-system.cpu6: completed 10000 read accesses @26653472
-system.cpu1: completed 10000 read accesses @27123929
-system.cpu2: completed 10000 read accesses @27264228
-system.cpu5: completed 10000 read accesses @27378204
-system.cpu3: completed 10000 read accesses @27427879
-system.cpu7: completed 10000 read accesses @27467412
-system.cpu4: completed 20000 read accesses @53181289
-system.cpu2: completed 20000 read accesses @53547298
-system.cpu0: completed 20000 read accesses @53713168
-system.cpu5: completed 20000 read accesses @54003765
-system.cpu6: completed 20000 read accesses @54078034
-system.cpu1: completed 20000 read accesses @54428010
-system.cpu7: completed 20000 read accesses @54428201
-system.cpu3: completed 20000 read accesses @54538530
-system.cpu2: completed 30000 read accesses @79806624
-system.cpu4: completed 30000 read accesses @80477319
-system.cpu0: completed 30000 read accesses @80890126
-system.cpu6: completed 30000 read accesses @80990962
-system.cpu5: completed 30000 read accesses @81492903
-system.cpu1: completed 30000 read accesses @81521875
-system.cpu7: completed 30000 read accesses @81619556
-system.cpu3: completed 30000 read accesses @82646612
-system.cpu2: completed 40000 read accesses @105920590
-system.cpu4: completed 40000 read accesses @106535590
-system.cpu0: completed 40000 read accesses @106901597
-system.cpu6: completed 40000 read accesses @107068434
-system.cpu5: completed 40000 read accesses @107463528
-system.cpu7: completed 40000 read accesses @108151860
-system.cpu1: completed 40000 read accesses @108295057
-system.cpu3: completed 40000 read accesses @109438245
-system.cpu2: completed 50000 read accesses @132968913
-system.cpu4: completed 50000 read accesses @133752042
-system.cpu0: completed 50000 read accesses @133897400
-system.cpu6: completed 50000 read accesses @134191909
-system.cpu5: completed 50000 read accesses @135041964
-system.cpu7: completed 50000 read accesses @135432848
-system.cpu1: completed 50000 read accesses @136127784
-system.cpu3: completed 50000 read accesses @137167267
-system.cpu2: completed 60000 read accesses @160901546
-system.cpu4: completed 60000 read accesses @161170032
-system.cpu6: completed 60000 read accesses @161540559
-system.cpu0: completed 60000 read accesses @161693235
-system.cpu5: completed 60000 read accesses @161854598
-system.cpu1: completed 60000 read accesses @163372166
-system.cpu7: completed 60000 read accesses @163560871
-system.cpu3: completed 60000 read accesses @163979808
-system.cpu2: completed 70000 read accesses @188319198
-system.cpu5: completed 70000 read accesses @188516414
-system.cpu4: completed 70000 read accesses @188575474
-system.cpu6: completed 70000 read accesses @188767860
-system.cpu0: completed 70000 read accesses @189199394
-system.cpu3: completed 70000 read accesses @191117524
-system.cpu7: completed 70000 read accesses @191140120
-system.cpu1: completed 70000 read accesses @191152245
-system.cpu2: completed 80000 read accesses @215320174
-system.cpu4: completed 80000 read accesses @215525158
-system.cpu6: completed 80000 read accesses @215775319
-system.cpu5: completed 80000 read accesses @215842805
-system.cpu0: completed 80000 read accesses @216807334
-system.cpu3: completed 80000 read accesses @218320776
-system.cpu1: completed 80000 read accesses @218370718
-system.cpu7: completed 80000 read accesses @218390295
-system.cpu2: completed 90000 read accesses @241936829
-system.cpu4: completed 90000 read accesses @242559490
-system.cpu6: completed 90000 read accesses @242752208
-system.cpu5: completed 90000 read accesses @242972513
-system.cpu0: completed 90000 read accesses @243685265
-system.cpu1: completed 90000 read accesses @244981315
-system.cpu3: completed 90000 read accesses @245492671
-system.cpu7: completed 90000 read accesses @245612294
-system.cpu2: completed 100000 read accesses @268782974
+system.cpu5: completed 10000 read accesses @25602084
+system.cpu0: completed 10000 read accesses @26185688
+system.cpu4: completed 10000 read accesses @26212882
+system.cpu3: completed 10000 read accesses @26366308
+system.cpu1: completed 10000 read accesses @26447108
+system.cpu7: completed 10000 read accesses @26537664
+system.cpu2: completed 10000 read accesses @26676832
+system.cpu6: completed 10000 read accesses @26707781
+system.cpu3: completed 20000 read accesses @51951998
+system.cpu5: completed 20000 read accesses @52231737
+system.cpu0: completed 20000 read accesses @52523512
+system.cpu4: completed 20000 read accesses @52614186
+system.cpu7: completed 20000 read accesses @52674871
+system.cpu1: completed 20000 read accesses @52986792
+system.cpu2: completed 20000 read accesses @53365626
+system.cpu6: completed 20000 read accesses @53537042
+system.cpu5: completed 30000 read accesses @78528098
+system.cpu3: completed 30000 read accesses @78636475
+system.cpu7: completed 30000 read accesses @79069859
+system.cpu0: completed 30000 read accesses @79082669
+system.cpu4: completed 30000 read accesses @79163244
+system.cpu6: completed 30000 read accesses @79592442
+system.cpu2: completed 30000 read accesses @79845712
+system.cpu1: completed 30000 read accesses @80286691
+system.cpu5: completed 40000 read accesses @103783596
+system.cpu0: completed 40000 read accesses @103983848
+system.cpu7: completed 40000 read accesses @104306510
+system.cpu3: completed 40000 read accesses @104792070
+system.cpu6: completed 40000 read accesses @104882247
+system.cpu4: completed 40000 read accesses @104921736
+system.cpu1: completed 40000 read accesses @105789168
+system.cpu2: completed 40000 read accesses @106255146
+system.cpu5: completed 50000 read accesses @130119835
+system.cpu0: completed 50000 read accesses @130621851
+system.cpu4: completed 50000 read accesses @131102250
+system.cpu7: completed 50000 read accesses @131131435
+system.cpu3: completed 50000 read accesses @131315326
+system.cpu6: completed 50000 read accesses @131463045
+system.cpu2: completed 50000 read accesses @132748289
+system.cpu1: completed 50000 read accesses @133533726
+system.cpu0: completed 60000 read accesses @157291050
+system.cpu5: completed 60000 read accesses @157331674
+system.cpu3: completed 60000 read accesses @157609229
+system.cpu4: completed 60000 read accesses @158092666
+system.cpu7: completed 60000 read accesses @158094050
+system.cpu6: completed 60000 read accesses @158284016
+system.cpu2: completed 60000 read accesses @159310066
+system.cpu1: completed 60000 read accesses @160315811
+system.cpu5: completed 70000 read accesses @184174146
+system.cpu0: completed 70000 read accesses @184194427
+system.cpu3: completed 70000 read accesses @184756116
+system.cpu7: completed 70000 read accesses @185107500
+system.cpu6: completed 70000 read accesses @185115722
+system.cpu4: completed 70000 read accesses @185437602
+system.cpu2: completed 70000 read accesses @186101472
+system.cpu1: completed 70000 read accesses @187053767
+system.cpu0: completed 80000 read accesses @210453706
+system.cpu7: completed 80000 read accesses @210994557
+system.cpu5: completed 80000 read accesses @211075215
+system.cpu3: completed 80000 read accesses @211165517
+system.cpu4: completed 80000 read accesses @211798954
+system.cpu6: completed 80000 read accesses @211876903
+system.cpu2: completed 80000 read accesses @212410812
+system.cpu1: completed 80000 read accesses @214554639
+system.cpu0: completed 90000 read accesses @236986702
+system.cpu5: completed 90000 read accesses @237258796
+system.cpu7: completed 90000 read accesses @237456793
+system.cpu4: completed 90000 read accesses @237741580
+system.cpu3: completed 90000 read accesses @237892702
+system.cpu6: completed 90000 read accesses @238620248
+system.cpu2: completed 90000 read accesses @239205755
+system.cpu1: completed 90000 read accesses @239913307
+system.cpu5: completed 100000 read accesses @263488655
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index d0c56eeac..073fadf83 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -7,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 26 2010 11:51:59
-M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
-M5 started Aug 26 2010 11:52:02
-M5 executing on zizzer
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:50:04
+M5 executing on phenom
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 268782974 because maximum number of loads reached
+Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 41d25a32a..54a425295 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,944 +1,944 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 330984                       # Number of bytes of host memory used
-host_seconds                                   227.97                       # Real time elapsed on the host
-host_tick_rate                                1179002                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318984                       # Number of bytes of host memory used
+host_seconds                                   150.28                       # Real time elapsed on the host
+host_tick_rate                                1753313                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.000269                       # Number of seconds simulated
-sim_ticks                                   268782974                       # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses                44543                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 36123.721103                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 35119.772902                       # average ReadReq mshr miss latency
+sim_seconds                                  0.000263                       # Number of seconds simulated
+sim_ticks                                   263488655                       # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses                44809                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373                       # average ReadReq mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits                     7515                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency       1337589145                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate            0.831287                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses                  37028                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency   1300414951                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831287                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses             37028                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    858196470                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses               24111                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 46338.684471                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 45334.813405                       # average WriteReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits                     7530                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency       1299667421                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate            0.831953                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses                  37279                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency   1262244251                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831953                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses             37279                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    894578632                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007                       # average WriteReq mshr miss latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits                    1045                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency      1068848096                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate           0.956659                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses                 23066                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency   1045692806                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956659                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses            23066                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    565288628                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3782.376120                       # average number of cycles each access was blocked
+system.cpu0.l1c.WriteReq_hits                    1059                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency      1001508092                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate           0.956350                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses                 23202                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency    978215253                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956350                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses            23202                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    569723237                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs                     0.409032                       # Average number of references to valid blocks.
-system.cpu0.l1c.blocked::no_mshrs               69095                       # number of cycles access was blocked
+system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
+system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_mshrs    261343278                       # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.demand_accesses                 68654                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency  40044.550887                       # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 39040.632293                       # average overall mshr miss latency
-system.cpu0.l1c.demand_hits                      8560                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency        2406437241                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate             0.875317                       # miss rate for demand accesses
-system.cpu0.l1c.demand_misses                   60094                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses                 69070                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency  38047.907822                       # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.demand_hits                      8589                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency        2301175513                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate             0.875648                       # miss rate for demand accesses
+system.cpu0.l1c.demand_misses                   60481                       # number of demand (read+write) misses
 system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency   2346107757                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate        0.875317                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses              60094                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency   2240459504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate        0.875648                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses              60481                       # number of demand (read+write) MSHR misses
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu0.l1c.occ_%::0                     0.677077                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_%::1                    -0.479198                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_blocks::0              346.663656                       # Average occupied blocks per context
-system.cpu0.l1c.occ_blocks::1             -245.349451                       # Average occupied blocks per context
-system.cpu0.l1c.overall_accesses                68654                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 40044.550887                       # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 39040.632293                       # average overall mshr miss latency
+system.cpu0.l1c.occ_%::0                     0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_%::1                    -0.477715                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
+system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
+system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits                     8560                       # number of overall hits
-system.cpu0.l1c.overall_miss_latency       2406437241                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate            0.875317                       # miss rate for overall accesses
-system.cpu0.l1c.overall_misses                  60094                       # number of overall misses
+system.cpu0.l1c.overall_hits                     8589                       # number of overall hits
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+system.cpu0.l1c.overall_miss_rate            0.875648                       # miss rate for overall accesses
+system.cpu0.l1c.overall_misses                  60481                       # number of overall misses
 system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency   2346107757                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate       0.875317                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses             60094                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency   1423485098                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_miss_latency   2240459504                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate       0.875648                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses             60481                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency   1464301869                       # number of overall MSHR uncacheable cycles
 system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.replacements                    27651                       # number of replacements
-system.cpu0.l1c.sampled_refs                    28010                       # Sample count of references to valid blocks.
+system.cpu0.l1c.replacements                    27826                       # number of replacements
+system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
 system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse                  101.314205                       # Cycle average of tags in use
-system.cpu0.l1c.total_refs                      11457                       # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse                  102.742005                       # Cycle average of tags in use
+system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
 system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks                      10896                       # number of writebacks
+system.cpu0.l1c.writebacks                      11972                       # number of writebacks
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99124                       # number of read accesses completed
-system.cpu0.num_writes                          53367                       # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses                44692                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 36448.304577                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 35444.437717                       # average ReadReq mshr miss latency
+system.cpu0.num_reads                           99815                       # number of read accesses completed
+system.cpu0.num_writes                          53929                       # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses                44539                       # number of ReadReq accesses(hits+misses)
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410                       # average ReadReq mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits                     7483                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency       1356204965                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate            0.832565                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses                  37209                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency   1318852083                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate       0.832565                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses             37209                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    832262163                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses               24176                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 46547.854438                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 45544.069690                       # average WriteReq mshr miss latency
+system.cpu1.l1c.ReadReq_hits                     7429                       # number of ReadReq hits
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+system.cpu1.l1c.ReadReq_miss_rate            0.833202                       # miss rate for ReadReq accesses
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+system.cpu1.l1c.ReadReq_mshr_miss_latency   1264508347                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833202                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses             37110                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    877119159                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses               24341                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825                       # average WriteReq mshr miss latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_hits                    1045                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency      1076698421                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate           0.956775                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses                 23131                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency   1053479876                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956775                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses            23131                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    547880829                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3789.476053                       # average number of cycles each access was blocked
+system.cpu1.l1c.WriteReq_hits                    1066                       # number of WriteReq hits
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+system.cpu1.l1c.WriteReq_mshr_miss_latency    990933889                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956206                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses            23275                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    578327433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs                     0.406952                       # Average number of references to valid blocks.
-system.cpu1.l1c.blocked::no_mshrs               69154                       # number of cycles access was blocked
+system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
+system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_mshrs    262057427                       # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.demand_accesses                 68868                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency  40319.910275                       # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 39316.074892                       # average overall mshr miss latency
-system.cpu1.l1c.demand_hits                      8528                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency        2432903386                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate             0.876169                       # miss rate for demand accesses
-system.cpu1.l1c.demand_misses                   60340                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_accesses                 68880                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency  38354.853291                       # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.demand_hits                      8495                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency        2316057816                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate             0.876670                       # miss rate for demand accesses
+system.cpu1.l1c.demand_misses                   60385                       # number of demand (read+write) misses
 system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency   2372331959                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate        0.876169                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses              60340                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_miss_latency   2255442236                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate        0.876670                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses              60385                       # number of demand (read+write) MSHR misses
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.l1c.occ_%::0                     0.676672                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_%::1                    -0.519109                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_blocks::0              346.455959                       # Average occupied blocks per context
-system.cpu1.l1c.occ_blocks::1             -265.783624                       # Average occupied blocks per context
-system.cpu1.l1c.overall_accesses                68868                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 40319.910275                       # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 39316.074892                       # average overall mshr miss latency
+system.cpu1.l1c.occ_%::0                     0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_%::1                    -0.493432                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
+system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
+system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits                     8528                       # number of overall hits
-system.cpu1.l1c.overall_miss_latency       2432903386                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate            0.876169                       # miss rate for overall accesses
-system.cpu1.l1c.overall_misses                  60340                       # number of overall misses
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+system.cpu1.l1c.overall_miss_latency       2316057816                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate            0.876670                       # miss rate for overall accesses
+system.cpu1.l1c.overall_misses                  60385                       # number of overall misses
 system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency   2372331959                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate       0.876169                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses             60340                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency   1380142992                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_miss_latency   2255442236                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate       0.876670                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses             60385                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency   1455446592                       # number of overall MSHR uncacheable cycles
 system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.replacements                    27809                       # number of replacements
-system.cpu1.l1c.sampled_refs                    28163                       # Sample count of references to valid blocks.
+system.cpu1.l1c.replacements                    27684                       # number of replacements
+system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
 system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse                   80.672335                       # Cycle average of tags in use
-system.cpu1.l1c.total_refs                      11461                       # Total number of references to valid blocks.
+system.cpu1.l1c.tagsinuse                   93.018974                       # Cycle average of tags in use
+system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
 system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks                      11031                       # number of writebacks
+system.cpu1.l1c.writebacks                      11809                       # number of writebacks
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           98655                       # number of read accesses completed
-system.cpu1.num_writes                          53481                       # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses                45038                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 36539.477136                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 35535.528785                       # average ReadReq mshr miss latency
+system.cpu1.num_reads                           98493                       # number of read accesses completed
+system.cpu1.num_writes                          53671                       # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses                44720                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684                       # average ReadReq mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_hits                     7709                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency       1363982142                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate            0.828833                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses                  37329                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency   1326505754                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate       0.828833                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses             37329                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    836681722                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses               23997                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 46378.263030                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 45374.567249                       # average WriteReq mshr miss latency
+system.cpu2.l1c.ReadReq_hits                     7576                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency       1302790562                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate            0.830590                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses                  37144                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency   1265501937                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830590                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses             37144                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    900513056                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses               23954                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409                       # average WriteReq mshr miss latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_hits                    1030                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency      1065169567                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate           0.957078                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses                 22967                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency   1042117686                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate      0.957078                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses            22967                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    541254032                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3784.557167                       # average number of cycles each access was blocked
+system.cpu2.l1c.WriteReq_hits                    1069                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency       991654869                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate           0.955373                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses                 22885                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency    968684322                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate      0.955373                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses            22885                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    566349170                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs                     0.422062                       # Average number of references to valid blocks.
-system.cpu2.l1c.blocked::no_mshrs               69096                       # number of cycles access was blocked
+system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
+system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_mshrs    261497762                       # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.demand_accesses                 69035                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency  40287.112064                       # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 39283.259918                       # average overall mshr miss latency
-system.cpu2.l1c.demand_hits                      8739                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency        2429151709                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate             0.873412                       # miss rate for demand accesses
-system.cpu2.l1c.demand_misses                   60296                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_accesses                 68674                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency  38222.283080                       # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.demand_hits                      8645                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency        2294445431                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate             0.874115                       # miss rate for demand accesses
+system.cpu2.l1c.demand_misses                   60029                       # number of demand (read+write) misses
 system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency   2368623440                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate        0.873412                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses              60296                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_miss_latency   2234186259                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate        0.874115                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses              60029                       # number of demand (read+write) MSHR misses
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.l1c.occ_%::0                     0.676850                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_%::1                    -0.478308                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_blocks::0              346.547072                       # Average occupied blocks per context
-system.cpu2.l1c.occ_blocks::1             -244.893619                       # Average occupied blocks per context
-system.cpu2.l1c.overall_accesses                69035                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 40287.112064                       # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 39283.259918                       # average overall mshr miss latency
+system.cpu2.l1c.occ_%::0                     0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_%::1                    -0.509877                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
+system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
+system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits                     8739                       # number of overall hits
-system.cpu2.l1c.overall_miss_latency       2429151709                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate            0.873412                       # miss rate for overall accesses
-system.cpu2.l1c.overall_misses                  60296                       # number of overall misses
+system.cpu2.l1c.overall_hits                     8645                       # number of overall hits
+system.cpu2.l1c.overall_miss_latency       2294445431                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate            0.874115                       # miss rate for overall accesses
+system.cpu2.l1c.overall_misses                  60029                       # number of overall misses
 system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency   2368623440                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate       0.873412                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses             60296                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency   1377935754                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_miss_latency   2234186259                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate       0.874115                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses             60029                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency   1466862226                       # number of overall MSHR uncacheable cycles
 system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.replacements                    27578                       # number of replacements
-system.cpu2.l1c.sampled_refs                    27939                       # Sample count of references to valid blocks.
+system.cpu2.l1c.replacements                    27627                       # number of replacements
+system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
 system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse                  101.653453                       # Cycle average of tags in use
-system.cpu2.l1c.total_refs                      11792                       # Total number of references to valid blocks.
+system.cpu2.l1c.tagsinuse                   84.373112                       # Cycle average of tags in use
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 system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks                      10810                       # number of writebacks
+system.cpu2.l1c.writebacks                      11784                       # number of writebacks
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                          100000                       # number of read accesses completed
-system.cpu2.num_writes                          53177                       # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses                44066                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 36663.733654                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 35659.896412                       # average ReadReq mshr miss latency
+system.cpu2.num_reads                           99149                       # number of read accesses completed
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+system.cpu3.l1c.ReadReq_accesses                44743                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970                       # average ReadReq mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_hits                     7527                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency       1339656164                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate            0.829188                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses                  36539                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency   1302976955                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate       0.829188                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses             36539                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    855113033                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses               24215                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 46306.357957                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 45302.529556                       # average WriteReq mshr miss latency
+system.cpu3.l1c.ReadReq_hits                     7552                       # number of ReadReq hits
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+system.cpu3.l1c.ReadReq_miss_rate            0.831214                       # miss rate for ReadReq accesses
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+system.cpu3.l1c.ReadReq_mshr_miss_latency   1274692143                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate       0.831214                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses             37191                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    889431937                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses               24297                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641                       # average WriteReq mshr miss latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_hits                    1039                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency      1073196152                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate           0.957093                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses                 23176                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency   1049931425                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate      0.957093                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses            23176                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    550326400                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3815.748803                       # average number of cycles each access was blocked
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+system.cpu3.l1c.WriteReq_mshr_miss_latency    972218785                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate      0.955632                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses            23219                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    569772276                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs                     0.416270                       # Average number of references to valid blocks.
-system.cpu3.l1c.blocked::no_mshrs               68739                       # number of cycles access was blocked
+system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
+system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_mshrs    262290757                       # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.demand_accesses                 68281                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency  40406.134405                       # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 39402.300594                       # average overall mshr miss latency
-system.cpu3.l1c.demand_hits                      8566                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency        2412852316                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate             0.874548                       # miss rate for demand accesses
-system.cpu3.l1c.demand_misses                   59715                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_accesses                 69040                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency  38198.189340                       # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.demand_hits                      8630                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency        2307552618                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate             0.875000                       # miss rate for demand accesses
+system.cpu3.l1c.demand_misses                   60410                       # number of demand (read+write) misses
 system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency   2352908380                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate        0.874548                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses              59715                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_miss_latency   2246910928                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate        0.875000                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses              60410                       # number of demand (read+write) MSHR misses
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.l1c.occ_%::0                     0.676162                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_%::1                    -0.498781                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_blocks::0              346.195007                       # Average occupied blocks per context
-system.cpu3.l1c.occ_blocks::1             -255.375812                       # Average occupied blocks per context
-system.cpu3.l1c.overall_accesses                68281                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 40406.134405                       # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 39402.300594                       # average overall mshr miss latency
+system.cpu3.l1c.occ_%::0                     0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_%::1                    -0.475386                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
+system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
+system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits                     8566                       # number of overall hits
-system.cpu3.l1c.overall_miss_latency       2412852316                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate            0.874548                       # miss rate for overall accesses
-system.cpu3.l1c.overall_misses                  59715                       # number of overall misses
+system.cpu3.l1c.overall_hits                     8630                       # number of overall hits
+system.cpu3.l1c.overall_miss_latency       2307552618                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate            0.875000                       # miss rate for overall accesses
+system.cpu3.l1c.overall_misses                  60410                       # number of overall misses
 system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency   2352908380                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate       0.874548                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses             59715                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency   1405439433                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_miss_latency   2246910928                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate       0.875000                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses             60410                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency   1459204213                       # number of overall MSHR uncacheable cycles
 system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.replacements                    27386                       # number of replacements
-system.cpu3.l1c.sampled_refs                    27732                       # Sample count of references to valid blocks.
+system.cpu3.l1c.replacements                    27837                       # number of replacements
+system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
 system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse                   90.819194                       # Cycle average of tags in use
-system.cpu3.l1c.total_refs                      11544                       # Total number of references to valid blocks.
+system.cpu3.l1c.tagsinuse                  104.177298                       # Cycle average of tags in use
+system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
 system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks                      11018                       # number of writebacks
+system.cpu3.l1c.writebacks                      11956                       # number of writebacks
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           98478                       # number of read accesses completed
-system.cpu3.num_writes                          53622                       # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses                45008                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 36033.874070                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 35030.059630                       # average ReadReq mshr miss latency
+system.cpu3.num_reads                           99588                       # number of read accesses completed
+system.cpu3.num_writes                          53645                       # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses                44937                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817                       # average ReadReq mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_hits                     7527                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency       1350585634                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate            0.832763                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses                  37481                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency   1312961665                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate       0.832763                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses             37481                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    847380535                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses               23997                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 46593.872314                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 45590.001874                       # average WriteReq mshr miss latency
+system.cpu4.l1c.ReadReq_hits                     7686                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency       1303112178                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate            0.828961                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses                  37251                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency   1265717116                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate       0.828961                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses             37251                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    898461911                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses               24060                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864                       # average WriteReq mshr miss latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_hits                    1050                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency      1069189588                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate           0.956245                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses                 22947                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency   1046153773                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate      0.956245                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses            22947                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    545030541                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3774.299862                       # average number of cycles each access was blocked
+system.cpu4.l1c.WriteReq_hits                    1123                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency       994450363                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate           0.953325                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses                 22937                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency    971425596                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate      0.953325                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses            22937                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    576408625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs                     0.407790                       # Average number of references to valid blocks.
-system.cpu4.l1c.blocked::no_mshrs               69472                       # number of cycles access was blocked
+system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
+system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_mshrs    262208160                       # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.demand_accesses                 69005                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency  40043.940259                       # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 39040.104554                       # average overall mshr miss latency
-system.cpu4.l1c.demand_hits                      8577                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency        2419775222                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate             0.875705                       # miss rate for demand accesses
-system.cpu4.l1c.demand_misses                   60428                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency  38173.099970                       # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.demand_hits                      8809                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency        2297562541                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate             0.872328                       # miss rate for demand accesses
+system.cpu4.l1c.demand_misses                   60188                       # number of demand (read+write) misses
 system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency   2359115438                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate        0.875705                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses              60428                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_miss_latency   2237142712                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate        0.872328                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.l1c.occ_%::0                     0.677776                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_%::1                    -0.492031                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_blocks::0              347.021071                       # Average occupied blocks per context
-system.cpu4.l1c.occ_blocks::1             -251.919968                       # Average occupied blocks per context
-system.cpu4.l1c.overall_accesses                69005                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 40043.940259                       # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 39040.104554                       # average overall mshr miss latency
+system.cpu4.l1c.occ_%::0                     0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_%::1                    -0.494043                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
+system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
+system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits                     8577                       # number of overall hits
-system.cpu4.l1c.overall_miss_latency       2419775222                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate            0.875705                       # miss rate for overall accesses
-system.cpu4.l1c.overall_misses                  60428                       # number of overall misses
+system.cpu4.l1c.overall_hits                     8809                       # number of overall hits
+system.cpu4.l1c.overall_miss_latency       2297562541                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate            0.872328                       # miss rate for overall accesses
+system.cpu4.l1c.overall_misses                  60188                       # number of overall misses
 system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency   2359115438                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate       0.875705                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses             60428                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency   1392411076                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_miss_latency   2237142712                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate       0.872328                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency   1474870536                       # number of overall MSHR uncacheable cycles
 system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.replacements                    27777                       # number of replacements
-system.cpu4.l1c.sampled_refs                    28137                       # Sample count of references to valid blocks.
+system.cpu4.l1c.replacements                    27683                       # number of replacements
+system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
 system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse                   95.101103                       # Cycle average of tags in use
-system.cpu4.l1c.total_refs                      11474                       # Total number of references to valid blocks.
+system.cpu4.l1c.tagsinuse                   94.681644                       # Cycle average of tags in use
+system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
 system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks                      10886                       # number of writebacks
+system.cpu4.l1c.writebacks                      11763                       # number of writebacks
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99551                       # number of read accesses completed
-system.cpu4.num_writes                          53296                       # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses                44744                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 36368.758988                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 35364.864697                       # average ReadReq mshr miss latency
+system.cpu4.num_reads                           99725                       # number of read accesses completed
+system.cpu4.num_writes                          53533                       # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses                44941                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160                       # average ReadReq mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_hits                     7472                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency       1355536385                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate            0.833006                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses                  37272                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency   1318119237                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate       0.833006                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses             37272                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    852691241                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses               23986                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 46171.822983                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 45167.996249                       # average WriteReq mshr miss latency
+system.cpu5.l1c.ReadReq_hits                     7592                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency       1291933371                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate            0.831067                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses                  37349                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency   1254436910                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831067                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses             37349                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    902856034                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses               24139                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397                       # average WriteReq mshr miss latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_hits                    1056                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency      1058719901                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate           0.955974                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses                 22930                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency   1035702154                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate      0.955974                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses            22930                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    557751081                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3778.589914                       # average number of cycles each access was blocked
+system.cpu5.l1c.WriteReq_hits                    1126                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency       998304045                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate           0.953353                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses                 23013                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency    975203983                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate      0.953353                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses            23013                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    567587171                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs                     0.409325                       # Average number of references to valid blocks.
-system.cpu5.l1c.blocked::no_mshrs               69283                       # number of cycles access was blocked
+system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
+system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_mshrs    261792045                       # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.demand_accesses                 68730                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency  40102.592705                       # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 39098.724145                       # average overall mshr miss latency
-system.cpu5.l1c.demand_hits                      8528                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency        2414256286                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate             0.875920                       # miss rate for demand accesses
-system.cpu5.l1c.demand_misses                   60202                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_accesses                 69080                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency  37941.708625                       # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.demand_hits                      8718                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency        2290237416                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate             0.873798                       # miss rate for demand accesses
+system.cpu5.l1c.demand_misses                   60362                       # number of demand (read+write) misses
 system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency   2353821391                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate        0.875920                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses              60202                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_miss_latency   2229640893                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate        0.873798                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses              60362                       # number of demand (read+write) MSHR misses
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.l1c.occ_%::0                     0.676586                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_%::1                    -0.517786                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_blocks::0              346.411919                       # Average occupied blocks per context
-system.cpu5.l1c.occ_blocks::1             -265.106244                       # Average occupied blocks per context
-system.cpu5.l1c.overall_accesses                68730                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 40102.592705                       # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 39098.724145                       # average overall mshr miss latency
+system.cpu5.l1c.occ_%::0                     0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_%::1                    -0.494726                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
+system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
+system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits                     8528                       # number of overall hits
-system.cpu5.l1c.overall_miss_latency       2414256286                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate            0.875920                       # miss rate for overall accesses
-system.cpu5.l1c.overall_misses                  60202                       # number of overall misses
+system.cpu5.l1c.overall_hits                     8718                       # number of overall hits
+system.cpu5.l1c.overall_miss_latency       2290237416                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate            0.873798                       # miss rate for overall accesses
+system.cpu5.l1c.overall_misses                  60362                       # number of overall misses
 system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency   2353821391                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate       0.875920                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses             60202                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency   1410442322                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_miss_latency   2229640893                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate       0.873798                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses             60362                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency   1470443205                       # number of overall MSHR uncacheable cycles
 system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.replacements                    27648                       # number of replacements
-system.cpu5.l1c.sampled_refs                    28012                       # Sample count of references to valid blocks.
+system.cpu5.l1c.replacements                    27832                       # number of replacements
+system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
 system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse                   81.305675                       # Cycle average of tags in use
-system.cpu5.l1c.total_refs                      11466                       # Total number of references to valid blocks.
+system.cpu5.l1c.tagsinuse                   93.507234                       # Cycle average of tags in use
+system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
 system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks                      10733                       # number of writebacks
+system.cpu5.l1c.writebacks                      11908                       # number of writebacks
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99169                       # number of read accesses completed
-system.cpu5.num_writes                          53407                       # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses                44448                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 36132.726042                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 35128.832255                       # average ReadReq mshr miss latency
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53710                       # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses                44652                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723                       # average ReadReq mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_hits                     7362                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency       1340018278                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate            0.834368                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses                  37086                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency   1302787873                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate       0.834368                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses             37086                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    855211413                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses               24069                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 46585.122881                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 45581.252108                       # average WriteReq mshr miss latency
+system.cpu6.l1c.ReadReq_hits                     7543                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency       1299799162                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate            0.831071                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses                  37109                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency   1262548698                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate       0.831071                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses             37109                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    877981455                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809                       # average WriteReq mshr miss latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_hits                    1063                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency      1071737337                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate           0.955835                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses                 23006                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency   1048642286                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate      0.955835                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses            23006                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    544765056                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3789.464275                       # average number of cycles each access was blocked
+system.cpu6.l1c.WriteReq_hits                    1119                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency      1015775810                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate           0.953877                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses                 23142                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency    992541214                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate      0.953877                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses            23142                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    574689009                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs                     0.404372                       # Average number of references to valid blocks.
-system.cpu6.l1c.blocked::no_mshrs               69181                       # number of cycles access was blocked
+system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
+system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_mshrs    262158928                       # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.demand_accesses                 68517                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency  40134.387522                       # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 39130.502546                       # average overall mshr miss latency
-system.cpu6.l1c.demand_hits                      8425                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency        2411755615                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate             0.877038                       # miss rate for demand accesses
-system.cpu6.l1c.demand_misses                   60092                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_accesses                 68913                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency  38432.141740                       # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.demand_hits                      8662                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency        2315574972                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate             0.874305                       # miss rate for demand accesses
+system.cpu6.l1c.demand_misses                   60251                       # number of demand (read+write) misses
 system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency   2351430159                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate        0.877038                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses              60092                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_miss_latency   2255089912                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate        0.874305                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses              60251                       # number of demand (read+write) MSHR misses
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.l1c.occ_%::0                     0.677801                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_%::1                    -0.496036                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_blocks::0              347.034179                       # Average occupied blocks per context
-system.cpu6.l1c.occ_blocks::1             -253.970364                       # Average occupied blocks per context
-system.cpu6.l1c.overall_accesses                68517                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 40134.387522                       # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 39130.502546                       # average overall mshr miss latency
+system.cpu6.l1c.occ_%::0                     0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_%::1                    -0.502932                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
+system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
+system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits                     8425                       # number of overall hits
-system.cpu6.l1c.overall_miss_latency       2411755615                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate            0.877038                       # miss rate for overall accesses
-system.cpu6.l1c.overall_misses                  60092                       # number of overall misses
+system.cpu6.l1c.overall_hits                     8662                       # number of overall hits
+system.cpu6.l1c.overall_miss_latency       2315574972                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate            0.874305                       # miss rate for overall accesses
+system.cpu6.l1c.overall_misses                  60251                       # number of overall misses
 system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency   2351430159                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate       0.877038                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses             60092                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency   1399976469                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_miss_latency   2255089912                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate       0.874305                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses             60251                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency   1452670464                       # number of overall MSHR uncacheable cycles
 system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.replacements                    27727                       # number of replacements
-system.cpu6.l1c.sampled_refs                    28088                       # Sample count of references to valid blocks.
+system.cpu6.l1c.replacements                    27861                       # number of replacements
+system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
 system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse                   93.063815                       # Cycle average of tags in use
-system.cpu6.l1c.total_refs                      11358                       # Total number of references to valid blocks.
+system.cpu6.l1c.tagsinuse                   89.788098                       # Cycle average of tags in use
+system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
 system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks                      10914                       # number of writebacks
+system.cpu6.l1c.writebacks                      11849                       # number of writebacks
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99683                       # number of read accesses completed
-system.cpu6.num_writes                          53523                       # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses                44337                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 36522.690669                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 35518.851968                       # average ReadReq mshr miss latency
+system.cpu6.num_reads                           99389                       # number of read accesses completed
+system.cpu6.num_writes                          53686                       # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses                44748                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764                       # average ReadReq mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_hits                     7480                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency       1346116810                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate            0.831292                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses                  36857                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency   1309118327                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate       0.831292                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses             36857                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    838959921                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses               24343                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 46424.783164                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 45420.867730                       # average WriteReq mshr miss latency
+system.cpu7.l1c.ReadReq_hits                     7593                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency       1287127315                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate            0.830316                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses                  37155                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency   1249829653                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate       0.830316                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses             37155                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    901961636                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses               24232                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466                       # average WriteReq mshr miss latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_hits                    1012                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency      1083136616                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate           0.958427                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses                 23331                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency   1059714265                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate      0.958427                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses            23331                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    540840211                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3796.000043                       # average number of cycles each access was blocked
+system.cpu7.l1c.WriteReq_hits                    1111                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency      1006139538                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate           0.954152                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses                 23121                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency    982928032                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate      0.954152                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses            23121                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    558194703                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs                     0.416064                       # Average number of references to valid blocks.
-system.cpu7.l1c.blocked::no_mshrs               69142                       # number of cycles access was blocked
+system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
+system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_mshrs    262463035                       # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.demand_accesses                 68680                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency  40361.092344                       # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 39357.223898                       # average overall mshr miss latency
-system.cpu7.l1c.demand_hits                      8492                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency        2429253426                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate             0.876354                       # miss rate for demand accesses
-system.cpu7.l1c.demand_misses                   60188                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_accesses                 68980                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency  38046.102147                       # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.demand_hits                      8704                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency        2293266853                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate             0.873818                       # miss rate for demand accesses
+system.cpu7.l1c.demand_misses                   60276                       # number of demand (read+write) misses
 system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency   2368832592                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate        0.876354                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_miss_latency   2232757685                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate        0.873818                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses              60276                       # number of demand (read+write) MSHR misses
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.l1c.occ_%::0                     0.674827                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_%::1                    -0.513462                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_blocks::0              345.511223                       # Average occupied blocks per context
-system.cpu7.l1c.occ_blocks::1             -262.892483                       # Average occupied blocks per context
-system.cpu7.l1c.overall_accesses                68680                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 40361.092344                       # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 39357.223898                       # average overall mshr miss latency
+system.cpu7.l1c.occ_%::0                     0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_%::1                    -0.511413                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
+system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
+system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits                     8492                       # number of overall hits
-system.cpu7.l1c.overall_miss_latency       2429253426                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate            0.876354                       # miss rate for overall accesses
-system.cpu7.l1c.overall_misses                  60188                       # number of overall misses
+system.cpu7.l1c.overall_hits                     8704                       # number of overall hits
+system.cpu7.l1c.overall_miss_latency       2293266853                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate            0.873818                       # miss rate for overall accesses
+system.cpu7.l1c.overall_misses                  60276                       # number of overall misses
 system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency   2368832592                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate       0.876354                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency   1379800132                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_miss_latency   2232757685                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate       0.873818                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses             60276                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency   1460156339                       # number of overall MSHR uncacheable cycles
 system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.replacements                    27465                       # number of replacements
-system.cpu7.l1c.sampled_refs                    27801                       # Sample count of references to valid blocks.
+system.cpu7.l1c.replacements                    27727                       # number of replacements
+system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
 system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse                   82.618740                       # Cycle average of tags in use
-system.cpu7.l1c.total_refs                      11567                       # Total number of references to valid blocks.
+system.cpu7.l1c.tagsinuse                   84.250612                       # Cycle average of tags in use
+system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
 system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks                      10979                       # number of writebacks
+system.cpu7.l1c.writebacks                      11797                       # number of writebacks
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           98421                       # number of read accesses completed
-system.cpu7.num_writes                          53590                       # number of write accesses completed
-system.l2c.ReadExReq_accesses::0                 9369                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                 9394                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                 9196                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total            74717                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 398260.224036                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 396016.805392                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 405312.464104                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 397509.598950                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::4 399391.492087                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::5 403926.306566                       # average ReadExReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::7 394166.506608                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 3191078.805424                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40001.724786                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                     1955                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                     1938                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::2                     1911                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total                15493                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          2952701301                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.791333                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.793698                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2            0.792192                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3            0.797424                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::4            0.792220                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::5            0.790698                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::6            0.792234                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::7            0.791359                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        6.341158                       # miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_misses::total              59224                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits                    546                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency     2347221207                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       6.262995                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       6.246327                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2       6.380818                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3       6.299302                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::4       6.287827                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::5       6.346998                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::6       6.242340                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::7       6.198817                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total    50.265425                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadReq_accesses::0                  17167                       # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total             137697                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   404610.500772                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   394067.785201                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   392103.013129                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   400149.903324                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::4   398056.998482                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::5   392037.858092                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::6   398124.169760                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::7   399810.850703                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 3178961.079464                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40000.752102                       # average ReadReq mshr miss latency
+system.cpu7.num_reads                           99694                       # number of read accesses completed
+system.cpu7.num_writes                          53501                       # number of write accesses completed
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+system.l2c.ReadExReq_avg_miss_latency::1 385121.964187                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 409218.508599                       # average ReadExReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344                       # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_mshr_miss_rate::0       5.305091                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       5.145821                       # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::4       5.268573                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::5       5.262328                       # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::7       5.188523                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total    41.935906                       # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadReq_accesses::total             124904                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   395853.498935                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::2   395088.268896                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   391306.072181                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::4   393566.650298                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::7   409085.591473                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 3175882.758128                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                      11336                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                      11287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                      11416                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                      11146                       # number of ReadReq hits
-system.l2c.ReadReq_hits::4                      11284                       # number of ReadReq hits
-system.l2c.ReadReq_hits::5                      11333                       # number of ReadReq hits
-system.l2c.ReadReq_hits::6                      11105                       # number of ReadReq hits
-system.l2c.ReadReq_hits::7                      11287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  90194                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency            2359283830                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.339663                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.346590                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.345150                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.345969                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::4              0.344373                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::5              0.346839                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::6              0.347954                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::7              0.343321                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          2.759859                       # miss rate for ReadReq accesses
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-system.l2c.ReadReq_misses::1                     5987                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                     6017                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                     5896                       # number of ReadReq misses
-system.l2c.ReadReq_misses::4                     5927                       # number of ReadReq misses
-system.l2c.ReadReq_misses::5                     6018                       # number of ReadReq misses
-system.l2c.ReadReq_misses::6                     5926                       # number of ReadReq misses
-system.l2c.ReadReq_misses::7                     5901                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                47503                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                     1000                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency       1860154975                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         2.708860                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.692081                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         2.667527                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3         2.728729                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::4         2.701935                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::5         2.680134                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::6         2.730491                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::7         2.705550                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total    21.615307                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                  46503                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency   3178879082                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0                2136                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                2178                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                2231                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                2193                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::4                2115                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::5                2135                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::6                2103                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::7                2206                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           17297                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 176402.667868                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 172466.495596                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 171159.931235                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 169676.742923                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::4 174412.376485                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::5 178006.328485                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::6 177898.511205                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::7 168315.439542                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1388338.493339                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 39999.820703                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                     471                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     475                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::2                     515                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::3                     462                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::4                     431                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::5                     485                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::6                     452                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::7                     461                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3752                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency          293710442                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.779494                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.781910                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2           0.769162                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3           0.789330                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::4           0.796217                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::5           0.772834                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::6           0.785069                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::7           0.791024                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       6.265041                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                  1665                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1703                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                  1716                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                  1731                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::4                  1684                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::5                  1650                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::6                  1651                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::7                  1745                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             13545                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_hits                    59                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_miss_latency     539437582                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      6.313670                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      6.191919                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2      6.044823                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3      6.149567                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::4      6.376359                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::5      6.316628                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::6      6.412744                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::7      6.113327                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total    49.919037                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               13486                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_hits::0                      10466                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                      10370                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                      10579                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                      10469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::4                      10390                       # number of ReadReq hits
+system.l2c.ReadReq_hits::5                      10384                       # number of ReadReq hits
+system.l2c.ReadReq_hits::6                      10590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::7                      10463                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency            2043791615                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.330347                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.333376                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.328403                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.332845                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::4              0.333248                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::5              0.329978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::6              0.326978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::7              0.323177                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          2.638352                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                     5163                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     5186                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                     5173                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                     5223                       # number of ReadReq misses
+system.l2c.ReadReq_misses::4                     5193                       # number of ReadReq misses
+system.l2c.ReadReq_misses::5                     5114                       # number of ReadReq misses
+system.l2c.ReadReq_misses::6                     5145                       # number of ReadReq misses
+system.l2c.ReadReq_misses::7                     4996                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                      961                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency       1609227416                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         2.574189                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         2.586269                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         2.554088                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         2.563854                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::4         2.581788                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::5         2.595948                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::6         2.556848                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::7         2.602497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total    20.615481                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                  40232                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency   3189139994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses::0                2101                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                2017                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                2063                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                2073                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::4                2016                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::5                2089                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::6                2039                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::7                1993                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           16391                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                     457                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     419                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::2                     446                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::3                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::4                     430                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::5                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::6                     415                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::7                     411                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency          261408598                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.782485                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.792266                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2           0.783810                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3           0.776652                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::4           0.786706                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::5           0.778363                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::6           0.796469                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::7           0.793778                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       6.290529                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  1644                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                  1598                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                  1617                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                  1610                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::4                  1586                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::5                  1626                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::6                  1624                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::7                  1582                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_hits                    49                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_miss_latency     513507057                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      6.110424                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      6.364898                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2      6.222976                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3      6.192957                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::4      6.368056                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::5      6.145524                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::6      6.296224                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::7      6.441545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total    50.142604                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses               12838                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1717678292                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0                86531                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            86531                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                    86531                       # number of Writeback hits
-system.l2c.Writeback_hits::total                86531                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1723903484                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0                94038                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                    94038                       # number of Writeback hits
+system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.997257                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                   26536                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                   26668                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                   26629                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                   26357                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::4                   26543                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::5                   26596                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::6                   26431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::7                   26654                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              212414                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    401055.880030                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    395148.786060                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    399337.327545                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3    398677.959397                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::4    398797.682508                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::5    398558.308148                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::6    397217.163763                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::7    396653.608946                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3185446.716395                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40001.294740                       # average overall mshr miss latency
-system.l2c.demand_hits::0                       13291                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                       13225                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                       13327                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                       13033                       # number of demand (read+write) hits
-system.l2c.demand_hits::4                       13223                       # number of demand (read+write) hits
-system.l2c.demand_hits::5                       13268                       # number of demand (read+write) hits
-system.l2c.demand_hits::6                       13058                       # number of demand (read+write) hits
-system.l2c.demand_hits::7                       13262                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  105687                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency             5311985131                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.499133                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.504087                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.499531                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.505520                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::4               0.501827                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::5               0.501128                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::6               0.505959                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::7               0.502439                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           4.019624                       # miss rate for demand accesses
-system.l2c.demand_misses::0                     13245                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     13443                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                     13302                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                     13324                       # number of demand (read+write) misses
-system.l2c.demand_misses::4                     13320                       # number of demand (read+write) misses
-system.l2c.demand_misses::5                     13328                       # number of demand (read+write) misses
-system.l2c.demand_misses::6                     13373                       # number of demand (read+write) misses
-system.l2c.demand_misses::7                     13392                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                106727                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                      1546                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency        4207376182                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          3.963710                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          3.944090                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          3.949867                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3          3.990629                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::4          3.962664                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::5          3.954768                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::6          3.979456                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::7          3.946162                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     31.691345                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  105181                       # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses::0                   23997                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    399979.441506                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    389356.010824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    397786.449494                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::4    396643.808655                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::5    403029.844930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::6    391099.130471                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::7    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  39999.713489                       # average overall mshr miss latency
+system.l2c.demand_hits::0                       13295                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                       13189                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                       13480                       # number of demand (read+write) hits
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+system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency             4280579983                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.445972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.454617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.441105                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.448468                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::4               0.449498                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::5               0.443762                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::6               0.448253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::7               0.443015                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           3.574690                       # miss rate for demand accesses
+system.l2c.demand_misses::0                     10702                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     10994                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                     10761                       # number of demand (read+write) misses
+system.l2c.demand_misses::4                     10792                       # number of demand (read+write) misses
+system.l2c.demand_misses::5                     10621                       # number of demand (read+write) misses
+system.l2c.demand_misses::6                     10945                       # number of demand (read+write) misses
+system.l2c.demand_misses::7                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                      1468                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency        3384975754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          3.526482                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          3.499359                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          3.508645                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3          3.526776                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::4          3.524720                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::5          3.535765                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::6          3.465823                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::7          3.523839                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total     28.111410                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                   84625                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.025373                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.025977                       # Average percentage of cache occupancy
-system.l2c.occ_%::2                          0.026279                       # Average percentage of cache occupancy
-system.l2c.occ_%::3                          0.025685                       # Average percentage of cache occupancy
-system.l2c.occ_%::4                          0.025981                       # Average percentage of cache occupancy
-system.l2c.occ_%::5                          0.026528                       # Average percentage of cache occupancy
-system.l2c.occ_%::6                          0.026219                       # Average percentage of cache occupancy
-system.l2c.occ_%::7                          0.025911                       # Average percentage of cache occupancy
-system.l2c.occ_%::8                          0.410377                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                    25.981879                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    26.600597                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                    26.909195                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                    26.301014                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                    26.604829                       # Average occupied blocks per context
-system.l2c.occ_blocks::5                    27.164696                       # Average occupied blocks per context
-system.l2c.occ_blocks::6                    26.848001                       # Average occupied blocks per context
-system.l2c.occ_blocks::7                    26.532744                       # Average occupied blocks per context
-system.l2c.occ_blocks::8                   420.226520                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                  26536                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                  26668                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                  26629                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                  26357                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::4                  26543                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::5                  26596                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::6                  26431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::7                  26654                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             212414                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   401055.880030                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   395148.786060                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   399337.327545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3   398677.959397                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::4   398797.682508                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::5   398558.308148                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::6   397217.163763                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::7   396653.608946                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3185446.716395                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40001.294740                       # average overall mshr miss latency
+system.l2c.occ_%::0                          0.023513                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.023339                       # Average percentage of cache occupancy
+system.l2c.occ_%::2                          0.023014                       # Average percentage of cache occupancy
+system.l2c.occ_%::3                          0.023888                       # Average percentage of cache occupancy
+system.l2c.occ_%::4                          0.023463                       # Average percentage of cache occupancy
+system.l2c.occ_%::5                          0.022624                       # Average percentage of cache occupancy
+system.l2c.occ_%::6                          0.022944                       # Average percentage of cache occupancy
+system.l2c.occ_%::7                          0.022464                       # Average percentage of cache occupancy
+system.l2c.occ_%::8                          0.457051                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                    24.461210                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                    24.025606                       # Average occupied blocks per context
+system.l2c.occ_blocks::5                    23.167376                       # Average occupied blocks per context
+system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
+system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
+system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                  23995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::4                  24009                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::5                  23934                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::6                  24417                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::7                  24015                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   399979.441506                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   389356.010824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   397786.449494                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::4   396643.808655                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::5   403029.844930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::6   391099.130471                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::7   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 39999.713489                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                      13291                       # number of overall hits
-system.l2c.overall_hits::1                      13225                       # number of overall hits
-system.l2c.overall_hits::2                      13327                       # number of overall hits
-system.l2c.overall_hits::3                      13033                       # number of overall hits
-system.l2c.overall_hits::4                      13223                       # number of overall hits
-system.l2c.overall_hits::5                      13268                       # number of overall hits
-system.l2c.overall_hits::6                      13058                       # number of overall hits
-system.l2c.overall_hits::7                      13262                       # number of overall hits
-system.l2c.overall_hits::total                 105687                       # number of overall hits
-system.l2c.overall_miss_latency            5311985131                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.499133                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.504087                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.499531                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.505520                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::4              0.501827                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::5              0.501128                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::6              0.505959                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::7              0.502439                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          4.019624                       # miss rate for overall accesses
-system.l2c.overall_misses::0                    13245                       # number of overall misses
-system.l2c.overall_misses::1                    13443                       # number of overall misses
-system.l2c.overall_misses::2                    13302                       # number of overall misses
-system.l2c.overall_misses::3                    13324                       # number of overall misses
-system.l2c.overall_misses::4                    13320                       # number of overall misses
-system.l2c.overall_misses::5                    13328                       # number of overall misses
-system.l2c.overall_misses::6                    13373                       # number of overall misses
-system.l2c.overall_misses::7                    13392                       # number of overall misses
-system.l2c.overall_misses::total               106727                       # number of overall misses
-system.l2c.overall_mshr_hits                     1546                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency       4207376182                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         3.963710                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         3.944090                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         3.949867                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3         3.990629                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::4         3.962664                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::5         3.954768                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::6         3.979456                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::7         3.946162                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    31.691345                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 105181                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   4896557374                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_hits::0                      13295                       # number of overall hits
+system.l2c.overall_hits::1                      13189                       # number of overall hits
+system.l2c.overall_hits::2                      13480                       # number of overall hits
+system.l2c.overall_hits::3                      13234                       # number of overall hits
+system.l2c.overall_hits::4                      13217                       # number of overall hits
+system.l2c.overall_hits::5                      13313                       # number of overall hits
+system.l2c.overall_hits::6                      13472                       # number of overall hits
+system.l2c.overall_hits::7                      13376                       # number of overall hits
+system.l2c.overall_hits::total                 106576                       # number of overall hits
+system.l2c.overall_miss_latency            4280579983                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.445972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.454617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.441105                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.448468                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::4              0.449498                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::5              0.443762                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::6              0.448253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::7              0.443015                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          3.574690                       # miss rate for overall accesses
+system.l2c.overall_misses::0                    10702                       # number of overall misses
+system.l2c.overall_misses::1                    10994                       # number of overall misses
+system.l2c.overall_misses::2                    10639                       # number of overall misses
+system.l2c.overall_misses::3                    10761                       # number of overall misses
+system.l2c.overall_misses::4                    10792                       # number of overall misses
+system.l2c.overall_misses::5                    10621                       # number of overall misses
+system.l2c.overall_misses::6                    10945                       # number of overall misses
+system.l2c.overall_misses::7                    10639                       # number of overall misses
+system.l2c.overall_misses::total                86093                       # number of overall misses
+system.l2c.overall_mshr_hits                     1468                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency       3384975754                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         3.526482                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         3.499359                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         3.508645                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3         3.526776                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::4         3.524720                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::5         3.535765                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::6         3.465823                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::7         3.523839                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total    28.111410                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                  84625                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   4913043478                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                         73319                       # number of replacements
-system.l2c.sampled_refs                         73994                       # Sample count of references to valid blocks.
+system.l2c.replacements                         76856                       # number of replacements
+system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                       633.169475                       # Cycle average of tags in use
-system.l2c.total_refs                          147785                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                       657.714518                       # Cycle average of tags in use
+system.l2c.total_refs                          139150                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                           46916                       # number of writebacks
+system.l2c.writebacks                           40644                       # number of writebacks
 
 ---------- End Simulation Statistics   ----------
-- 
2.30.2