From 13c739f273397ecc0e34a160aac15075760c748a Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 27 Jan 2020 09:34:40 -0500 Subject: [PATCH] FSGNJ: Replace use of Switch() with explicit muxes From http://bugs.libre-riscv.org/show_bug.cgi?id=120 "If(), Switch() and friends are fine for modules that are strictly scalar, but will not work if the module is converted to SIMD." --- src/ieee754/fsgnj/fsgnj.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py index dfb1df66..31501743 100644 --- a/src/ieee754/fsgnj/fsgnj.py +++ b/src/ieee754/fsgnj/fsgnj.py @@ -3,7 +3,7 @@ # Copyright (C) 2020 Michael Nolan -from nmigen import Module, Signal, Cat +from nmigen import Module, Signal, Cat, Mux from nmutil.pipemodbase import PipeModBase from ieee754.fpcommon.basedata import FPBaseData @@ -49,15 +49,9 @@ class FSGNJPipeMod(PipeModBase): sign = Signal() - with m.Switch(opcode): - with m.Case(0b00): - comb += sign.eq(b1.s) - with m.Case(0b01): - comb += sign.eq(~b1.s) - with m.Case(0b10): - comb += sign.eq(a1.s ^ b1.s) - with m.Default(): - comb += sign.eq(b1.s) + sign = Mux(opcode[0], ~b1.s, b1.s) + sign = Mux(opcode[1], sign ^ a1.s, sign) + comb += z1.eq(a1.fp.create2(sign, a1.e, a1.m)) -- 2.30.2