From 13e4d7c52556017227731e1289532582317049dc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 13:18:21 +0200
Subject: [PATCH] litescope: pep8 (E302)

---
 misoclib/tools/litescope/bridge/uart2wb.py                 | 3 +++
 misoclib/tools/litescope/common.py                         | 2 ++
 misoclib/tools/litescope/core/port.py                      | 6 ++++++
 misoclib/tools/litescope/core/storage.py                   | 6 ++++++
 misoclib/tools/litescope/core/trigger.py                   | 3 +++
 misoclib/tools/litescope/example_designs/make.py           | 2 ++
 misoclib/tools/litescope/example_designs/targets/simple.py | 1 +
 misoclib/tools/litescope/example_designs/test/make.py      | 1 +
 misoclib/tools/litescope/example_designs/test/test_io.py   | 3 +++
 misoclib/tools/litescope/example_designs/test/test_la.py   | 1 +
 misoclib/tools/litescope/frontend/io.py                    | 1 +
 misoclib/tools/litescope/frontend/la.py                    | 1 +
 misoclib/tools/litescope/host/driver/etherbone.py          | 1 +
 misoclib/tools/litescope/host/driver/la.py                 | 1 +
 misoclib/tools/litescope/host/driver/reg.py                | 5 ++++-
 misoclib/tools/litescope/host/driver/truthtable.py         | 6 ++++++
 misoclib/tools/litescope/host/driver/uart.py               | 2 ++
 misoclib/tools/litescope/host/dump/__init__.py             | 4 ++++
 misoclib/tools/litescope/host/dump/csv.py                  | 1 +
 misoclib/tools/litescope/host/dump/python.py               | 1 +
 misoclib/tools/litescope/host/dump/sigrok.py               | 1 +
 misoclib/tools/litescope/host/dump/vcd.py                  | 1 +
 22 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py
index fedb239c..88e5a9de 100644
--- a/misoclib/tools/litescope/bridge/uart2wb.py
+++ b/misoclib/tools/litescope/bridge/uart2wb.py
@@ -9,11 +9,13 @@ from migen.flow.actor import Sink, Source
 
 from misoclib.com.uart.phy.serial import UARTPHYSerial
 
+
 class UARTPads:
     def __init__(self):
         self.rx = Signal()
         self.tx = Signal()
 
+
 class UARTMux(Module):
     def __init__(self, pads):
         self.sel = Signal(max=2)
@@ -42,6 +44,7 @@ class UARTMux(Module):
                 pads.tx.eq(self.bridge_pads.tx)
             )
 
+
 class LiteScopeUART2WB(Module, AutoCSR):
     cmds = {
         "write"    : 0x01,
diff --git a/misoclib/tools/litescope/common.py b/misoclib/tools/litescope/common.py
index c39e3b59..51a4ca95 100644
--- a/misoclib/tools/litescope/common.py
+++ b/misoclib/tools/litescope/common.py
@@ -7,8 +7,10 @@ from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
 from migen.flow.plumbing import Buffer
 from migen.fhdl.specials import Memory
 
+
 def data_layout(dw):
     return [("data", dw, DIR_M_TO_S)]
 
+
 def hit_layout():
     return [("hit", 1, DIR_M_TO_S)]
diff --git a/misoclib/tools/litescope/core/port.py b/misoclib/tools/litescope/core/port.py
index dac82f44..91d702ef 100644
--- a/misoclib/tools/litescope/core/port.py
+++ b/misoclib/tools/litescope/core/port.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.common import *
 
+
 class LiteScopeTermUnit(Module):
     def __init__(self, dw):
         self.dw = dw
@@ -15,6 +16,7 @@ class LiteScopeTermUnit(Module):
             sink.ack.eq(source.ack)
         ]
 
+
 class LiteScopeTerm(LiteScopeTermUnit, AutoCSR):
     def __init__(self, dw):
         LiteScopeTermUnit.__init__(self, dw)
@@ -26,6 +28,7 @@ class LiteScopeTerm(LiteScopeTermUnit, AutoCSR):
             self.mask.eq(self._mask.storage)
         ]
 
+
 class LiteScopeRangeDetectorUnit(Module):
     def __init__(self, dw):
         self.dw = dw
@@ -41,6 +44,7 @@ class LiteScopeRangeDetectorUnit(Module):
             sink.ack.eq(source.ack)
         ]
 
+
 class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR):
     def __init__(self, dw):
         LiteScopeRangeDetectorUnit.__init__(self, dw)
@@ -52,6 +56,7 @@ class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR):
             self.high.eq(self._high.storage)
         ]
 
+
 class LiteScopeEdgeDetectorUnit(Module):
     def __init__(self, dw):
         self.dw = dw
@@ -80,6 +85,7 @@ class LiteScopeEdgeDetectorUnit(Module):
             source.hit.eq(rising | falling | both)
         ]
 
+
 class LiteScopeEdgeDetector(LiteScopeEdgeDetectorUnit, AutoCSR):
     def __init__(self, dw):
         LiteScopeEdgeDetectorUnit.__init__(self, dw)
diff --git a/misoclib/tools/litescope/core/storage.py b/misoclib/tools/litescope/core/storage.py
index baf0e7dc..df1cebc9 100644
--- a/misoclib/tools/litescope/core/storage.py
+++ b/misoclib/tools/litescope/core/storage.py
@@ -1,6 +1,7 @@
 from misoclib.tools.litescope.common import *
 from migen.flow.plumbing import Buffer
 
+
 class LiteScopeSubSamplerUnit(Module):
     def __init__(self, dw):
         self.sink = sink = Sink(data_layout(dw))
@@ -17,6 +18,7 @@ class LiteScopeSubSamplerUnit(Module):
             self.counter.reset.eq(source.stb & source.ack & done)
         ]
 
+
 class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
     def __init__(self, dw):
         LiteScopeSubSamplerUnit.__init__(self, dw)
@@ -24,6 +26,7 @@ class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
         ###
         self.comb += self.value.eq(self._value.storage)
 
+
 class LiteScopeRunLengthEncoderUnit(Module):
     def __init__(self, dw, length):
         self.dw = dw
@@ -73,6 +76,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
             )
         )
 
+
 class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
     def __init__(self, dw, length=1024):
         LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
@@ -81,6 +85,7 @@ class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
         ###
         self.comb += self.enable.eq(self._enable.storage & self.external_enable)
 
+
 class LiteScopeRecorderUnit(Module):
     def __init__(self, dw, depth):
         self.dw = dw
@@ -138,6 +143,7 @@ class LiteScopeRecorderUnit(Module):
             If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
         )
 
+
 class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
     def __init__(self, dw, depth):
         LiteScopeRecorderUnit.__init__(self, dw, depth)
diff --git a/misoclib/tools/litescope/core/trigger.py b/misoclib/tools/litescope/core/trigger.py
index bad11e4f..c5aee512 100644
--- a/misoclib/tools/litescope/core/trigger.py
+++ b/misoclib/tools/litescope/core/trigger.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.common import *
 
+
 class LiteScopeSumUnit(Module, AutoCSR):
     def __init__(self, ports):
         self.sinks = sinks = [Sink(hit_layout()) for i in range(ports)]
@@ -35,6 +36,7 @@ class LiteScopeSumUnit(Module, AutoCSR):
         for i, sink in enumerate(sinks):
             self.comb += sink.ack.eq(sink.stb & source.ack)
 
+
 class LiteScopeSum(LiteScopeSumUnit, AutoCSR):
     def __init__(self, ports):
         LiteScopeSumUnit.__init__(self, ports)
@@ -48,6 +50,7 @@ class LiteScopeSum(LiteScopeSumUnit, AutoCSR):
             self.prog_dat.eq(self._prog_dat.storage)
         ]
 
+
 class LiteScopeTrigger(Module, AutoCSR):
     def __init__(self, dw):
         self.dw = dw
diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py
index 7942f32c..fa77c62e 100644
--- a/misoclib/tools/litescope/example_designs/make.py
+++ b/misoclib/tools/litescope/example_designs/make.py
@@ -13,9 +13,11 @@ from mibuild.xilinx.common import *
 from misoclib.soc import cpuif
 from misoclib.tools.litescope.common import *
 
+
 def _import(default, name):
     return importlib.import_module(default + "." + name)
 
+
 def _get_args():
     parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
         description="""\
diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index 54a9659e..bd7897cf 100644
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -8,6 +8,7 @@ from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
+
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {
         "io":    16,
diff --git a/misoclib/tools/litescope/example_designs/test/make.py b/misoclib/tools/litescope/example_designs/test/make.py
index 1d3f2d9d..2c8bd783 100644
--- a/misoclib/tools/litescope/example_designs/test/make.py
+++ b/misoclib/tools/litescope/example_designs/test/make.py
@@ -1,6 +1,7 @@
 #!/usr/bin/env python3
 import argparse, importlib
 
+
 def _get_args():
     parser = argparse.ArgumentParser()
     parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
diff --git a/misoclib/tools/litescope/example_designs/test/test_io.py b/misoclib/tools/litescope/example_designs/test/test_io.py
index 28771ec6..9938480b 100644
--- a/misoclib/tools/litescope/example_designs/test/test_io.py
+++ b/misoclib/tools/litescope/example_designs/test/test_io.py
@@ -1,6 +1,7 @@
 import time
 from misoclib.tools.litescope.host.driver.io import LiteScopeIODriver
 
+
 def led_anim0(io):
     for i in range(10):
         io.write(0xA5)
@@ -8,6 +9,7 @@ def led_anim0(io):
         io.write(0x5A)
         time.sleep(0.1)
 
+
 def led_anim1(io):
     for j in range(4):
         #Led <<
@@ -23,6 +25,7 @@ def led_anim1(io):
             time.sleep(i*i*0.0020)
             led_data = (led_data>>1)
 
+
 def main(wb):
     io = LiteScopeIODriver(wb.regs, "io")
     wb.open()
diff --git a/misoclib/tools/litescope/example_designs/test/test_la.py b/misoclib/tools/litescope/example_designs/test/test_la.py
index e10c4933..f7422852 100644
--- a/misoclib/tools/litescope/example_designs/test/test_la.py
+++ b/misoclib/tools/litescope/example_designs/test/test_la.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.host.driver.la import LiteScopeLADriver
 
+
 def main(wb):
     wb.open()
     ###
diff --git a/misoclib/tools/litescope/frontend/io.py b/misoclib/tools/litescope/frontend/io.py
index 8a9be41e..2f4453eb 100644
--- a/misoclib/tools/litescope/frontend/io.py
+++ b/misoclib/tools/litescope/frontend/io.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.common import *
 
+
 class LiteScopeIO(Module, AutoCSR):
     def __init__(self, dw):
         self.dw = dw
diff --git a/misoclib/tools/litescope/frontend/la.py b/misoclib/tools/litescope/frontend/la.py
index 64d6bb08..a216c35b 100644
--- a/misoclib/tools/litescope/frontend/la.py
+++ b/misoclib/tools/litescope/frontend/la.py
@@ -4,6 +4,7 @@ from misoclib.tools.litescope.core.storage import LiteScopeSubSampler, LiteScope
 
 from mibuild.tools import write_to_file
 
+
 class LiteScopeLA(Module, AutoCSR):
     def __init__(self, layout, depth, clk_domain="sys",
             with_input_buffer=False,
diff --git a/misoclib/tools/litescope/host/driver/etherbone.py b/misoclib/tools/litescope/host/driver/etherbone.py
index 6359c460..d094bde1 100644
--- a/misoclib/tools/litescope/host/driver/etherbone.py
+++ b/misoclib/tools/litescope/host/driver/etherbone.py
@@ -3,6 +3,7 @@ from misoclib.tools.litescope.host.driver.reg import *
 
 from liteeth.test.model.etherbone import *
 
+
 class LiteScopeEtherboneDriver:
     def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
         self.ip_address = ip_address
diff --git a/misoclib/tools/litescope/host/driver/la.py b/misoclib/tools/litescope/host/driver/la.py
index b8af2526..a74eaf54 100644
--- a/misoclib/tools/litescope/host/driver/la.py
+++ b/misoclib/tools/litescope/host/driver/la.py
@@ -4,6 +4,7 @@ from migen.fhdl.structure import *
 from misoclib.tools.litescope.host.dump import *
 from misoclib.tools.litescope.host.driver.truthtable import *
 
+
 class LiteScopeLADriver():
     def __init__(self, regs, name, config_csv=None, clk_freq=None, debug=False):
         self.regs = regs
diff --git a/misoclib/tools/litescope/host/driver/reg.py b/misoclib/tools/litescope/host/driver/reg.py
index 71caa2ef..9c85c286 100644
--- a/misoclib/tools/litescope/host/driver/reg.py
+++ b/misoclib/tools/litescope/host/driver/reg.py
@@ -1,5 +1,6 @@
 import csv
 
+
 class MappedReg:
     def __init__(self, readfn, writefn, name, addr, length, busword, mode):
         self.readfn = readfn
@@ -36,6 +37,7 @@ class MappedReg:
             datas.append((value >> ((self.length-1-i)*self.busword)) & (2**self.busword-1))
         self.writefn(self.addr, datas)
 
+
 class MappedRegs:
     def __init__(self, d):
         self.d = d
@@ -47,7 +49,8 @@ class MappedRegs:
             pass
         raise KeyError("No such register " + attr)
 
-def    build_map(addrmap, busword, readfn, writefn):
+
+def build_map(addrmap, busword, readfn, writefn):
     csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
     d = {}
     for item in csv_reader:
diff --git a/misoclib/tools/litescope/host/driver/truthtable.py b/misoclib/tools/litescope/host/driver/truthtable.py
index 10d22066..5147f16d 100644
--- a/misoclib/tools/litescope/host/driver/truthtable.py
+++ b/misoclib/tools/litescope/host/driver/truthtable.py
@@ -2,6 +2,7 @@ import os
 import re
 import sys
 
+
 def is_number(x):
     try:
         _ = float(x)
@@ -9,20 +10,24 @@ def is_number(x):
         return False
     return True
 
+
 def remove_numbers(seq):
     return [x for x in seq if not is_number(x)]
 
+
 def remove_duplicates(seq):
     seen = set()
     seen_add = seen.add
     return [x for x in seq if x not in seen and not seen_add(x)]
 
+
 def get_operands(s):
     operands = re.findall("[A-z0-9_]+", s)
     operands = remove_duplicates(operands)
     operands = remove_numbers(operands)
     return sorted(operands)
 
+
 def gen_truth_table(s):
     operands = get_operands(s)
     width = len(operands)
@@ -40,6 +45,7 @@ def gen_truth_table(s):
         truth_table.append(eval(s) != 0)
     return truth_table
 
+
 def main():
     print(gen_truth_table("(A&B&C)|D"))
 
diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py
index 7d921e8c..4e36ca56 100644
--- a/misoclib/tools/litescope/host/driver/uart.py
+++ b/misoclib/tools/litescope/host/driver/uart.py
@@ -2,9 +2,11 @@ import serial
 from struct import *
 from misoclib.tools.litescope.host.driver.reg import *
 
+
 def write_b(uart, data):
     uart.write(pack('B',data))
 
+
 class LiteScopeUARTDriver:
     cmds = {
         "write"    : 0x01,
diff --git a/misoclib/tools/litescope/host/dump/__init__.py b/misoclib/tools/litescope/host/dump/__init__.py
index 070e27a6..db00ac7f 100644
--- a/misoclib/tools/litescope/host/dump/__init__.py
+++ b/misoclib/tools/litescope/host/dump/__init__.py
@@ -10,6 +10,7 @@ def dec2bin(d, nb=0):
             d=d>>1
     return b.zfill(nb)
 
+
 def get_bits(values, low, high=None):
     r = []
     if high is None:
@@ -19,6 +20,7 @@ def get_bits(values, low, high=None):
         r.append(t)
     return r
 
+
 class Dat(list):
     def __init__(self, width):
         self.width = width
@@ -57,6 +59,7 @@ class Dat(list):
                 last_data = data
         return datas
 
+
 class Var:
     def __init__(self, name, width, values=[], type="wire", default="x"):
         self.type = type
@@ -86,6 +89,7 @@ class Var:
             return r
         return r
 
+
 class Dump:
     def __init__(self):
         self.vars = []
diff --git a/misoclib/tools/litescope/host/dump/csv.py b/misoclib/tools/litescope/host/dump/csv.py
index db504c18..97209088 100644
--- a/misoclib/tools/litescope/host/dump/csv.py
+++ b/misoclib/tools/litescope/host/dump/csv.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.host.dump import *
 
+
 class CSVDump(Dump):
     def __init__(self, init_dump=None):
         Dump.__init__(self)
diff --git a/misoclib/tools/litescope/host/dump/python.py b/misoclib/tools/litescope/host/dump/python.py
index 4ff7fa06..b548f162 100644
--- a/misoclib/tools/litescope/host/dump/python.py
+++ b/misoclib/tools/litescope/host/dump/python.py
@@ -1,5 +1,6 @@
 from misoclib.tools.litescope.host.dump import *
 
+
 class PythonDump(Dump):
     def __init__(self, init_dump=None):
         Dump.__init__(self)
diff --git a/misoclib/tools/litescope/host/dump/sigrok.py b/misoclib/tools/litescope/host/dump/sigrok.py
index ab070b85..776c1c8d 100644
--- a/misoclib/tools/litescope/host/dump/sigrok.py
+++ b/misoclib/tools/litescope/host/dump/sigrok.py
@@ -7,6 +7,7 @@ from collections import OrderedDict
 
 from misoclib.tools.litescope.host.dump import *
 
+
 class SigrokDump(Dump):
     def __init__(self, init_dump=None, samplerate=50000000):
         Dump.__init__(self)
diff --git a/misoclib/tools/litescope/host/dump/vcd.py b/misoclib/tools/litescope/host/dump/vcd.py
index f6dd34bd..3b43a778 100644
--- a/misoclib/tools/litescope/host/dump/vcd.py
+++ b/misoclib/tools/litescope/host/dump/vcd.py
@@ -1,6 +1,7 @@
 import datetime
 from misoclib.tools.litescope.host.dump import *
 
+
 class VCDDump(Dump):
     def __init__(self, init_dump=None, timescale="1ps", comment=""):
         Dump.__init__(self)
-- 
2.30.2