From 13e84b0bbb7a0ce2bd935bf3c36e601f85c6f8b0 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 14 May 2020 14:26:14 +1000 Subject: [PATCH] pp_soc_uart: Fix rx synchronizers and ensure stable tx init state The rx synchronizers were ... non existent. Someone forgot to add a if rising_edge(clk) to the process. For tx, ensure that we have a default value so that TX stays high from TPGA configuration to the reset being sampled on the first clock cycle. Signed-off-by: Benjamin Herrenschmidt --- fpga/pp_soc_uart.vhd | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/fpga/pp_soc_uart.vhd b/fpga/pp_soc_uart.vhd index 429bec4..8c4c93c 100644 --- a/fpga/pp_soc_uart.vhd +++ b/fpga/pp_soc_uart.vhd @@ -111,6 +111,7 @@ architecture behaviour of pp_soc_uart is signal rxd2 : std_logic := '1'; signal rxd3 : std_logic := '1'; + signal txd2 : std_ulogic := '1'; begin irq <= (irq_recv_enable and (not recv_buffer_empty)) @@ -123,9 +124,12 @@ begin -- Add a few FFs on the RX input to avoid metastability issues process (clk) is begin - rxd3 <= rxd2; - rxd2 <= rxd; + if rising_edge(clk) then + rxd3 <= rxd2; + rxd2 <= rxd; + end if; end process; + txd <= txd2; uart_receive: process(clk) begin @@ -202,7 +206,7 @@ begin begin if rising_edge(clk) then if reset = '1' then - txd <= '1'; + txd2 <= '1'; tx_state <= IDLE; send_buffer_pop <= '0'; tx_current_bit <= 0; @@ -210,26 +214,26 @@ begin case tx_state is when IDLE => if send_buffer_empty = '0' and uart_tx_clk = '1' then - txd <= '0'; + txd2 <= '0'; send_buffer_pop <= '1'; tx_current_bit <= 0; tx_state <= TRANSMIT; elsif uart_tx_clk = '1' then - txd <= '1'; + txd2 <= '1'; end if; when TRANSMIT => if send_buffer_pop = '1' then send_buffer_pop <= '0'; elsif uart_tx_clk = '1' and tx_current_bit = 7 then - txd <= tx_byte(tx_current_bit); + txd2 <= tx_byte(tx_current_bit); tx_state <= STOPBIT; elsif uart_tx_clk = '1' then - txd <= tx_byte(tx_current_bit); + txd2 <= tx_byte(tx_current_bit); tx_current_bit <= tx_current_bit + 1; end if; when STOPBIT => if uart_tx_clk = '1' then - txd <= '1'; + txd2 <= '1'; tx_state <= IDLE; end if; end case; -- 2.30.2