From 141428e922554115331ea6ed90b10ee938566e93 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Mon, 3 Aug 2020 22:05:44 +0200 Subject: [PATCH] Add additional tests for sel signal --- gram/test/test_frontend_wishbone.py | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py index 27e83e9..51118a9 100644 --- a/gram/test/test_frontend_wishbone.py +++ b/gram/test/test_frontend_wishbone.py @@ -230,6 +230,12 @@ class GramWishboneTestCase(FHDLTestCase): self.assertEqual((yield native_port.wdata.we), 0b10000) def sel9(bus, native_port): self.assertEqual((yield native_port.wdata.we), 0b100000000) + def sel13(bus, native_port): + self.assertEqual((yield native_port.wdata.we), 0b1000000000000) + def selfirstdword(bus, native_port): + self.assertEqual((yield native_port.wdata.we), 0xF) + def sellastdword(bus, native_port): + self.assertEqual((yield native_port.wdata.we), 0xF000) yield from self.write_request(bus=dut.bus, native_port=native_port, @@ -279,4 +285,28 @@ class GramWishboneTestCase(FHDLTestCase): timeout=128, ackCallback=sel9) + yield from self.write_request(bus=dut.bus, + native_port=native_port, + adr=3, + sel=1, + value=0xCA, + timeout=128, + ackCallback=sel13) + + yield from self.write_request(bus=dut.bus, + native_port=native_port, + adr=3, + sel=0xF, + value=0xCA, + timeout=128, + ackCallback=sellastdword) + + yield from self.write_request(bus=dut.bus, + native_port=native_port, + adr=4, + sel=0xF, + value=0xCA, + timeout=128, + ackCallback=selfirstdword) + runSimulation(dut, process, "test_frontend_wishbone.vcd") -- 2.30.2