From 141ddb496b4e575723985d466a0936dc9172853a Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 11 Apr 2022 10:17:15 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 81d7a195b..1edb85af4 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -918,6 +918,10 @@ on a context-switch. This may make some implementations slower. *Implementor's Note: many SIMD-based Parallel Reduction Algorithms are implemented in hardware with MVs that ensure lane-crossing is minimised. +The mistake which would be catastrophic to SVP64 to make is to then +limit the Reduction Sequence for all implementors +based solely and exclusively on what one +specific internal microarchitecture does. In SIMD ISAs the internal SIMD Architectural design is exposed and imposed on the programmer. Cray-style Vector ISAs on the other hand provide convenient, compact and efficient encodings of abstract concepts. It is the Implementor's responsibility to produce a design -- 2.30.2