From 1425a68d9e68cd6af4508d4369512684d1b97138 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 24 Sep 2019 17:55:29 +0200 Subject: [PATCH] wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter. --- litex/soc/interconnect/wishbone2csr.py | 27 ++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py index 071e9676..b9544aad 100644 --- a/litex/soc/interconnect/wishbone2csr.py +++ b/litex/soc/interconnect/wishbone2csr.py @@ -1,5 +1,5 @@ # This file is Copyright (c) 2015 Sebastien Bourdeauducq -# This file is Copyright (c) 2015-2018 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from migen import * @@ -17,16 +17,23 @@ class WB2CSR(Module): bus_csr = csr_bus.Interface() self.csr = bus_csr - ### + # # # - self.sync += [ - self.csr.we.eq(0), + self.comb += [ self.csr.dat_w.eq(self.wishbone.dat_w), - self.csr.adr.eq(self.wishbone.adr), self.wishbone.dat_r.eq(self.csr.dat_r) ] - self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [ - (1, [self.csr.we.eq(self.wishbone.we)]), - (2, [self.wishbone.ack.eq(1)]), - (3, [self.wishbone.ack.eq(0)]) - ]) + + fsm = FSM(reset_state="WRITE-READ") + self.submodules += fsm + fsm.act("WRITE-READ", + If(self.wishbone.cyc & self.wishbone.stb, + self.csr.adr.eq(self.wishbone.adr), + self.csr.we.eq(self.wishbone.we), + NextState("ACK") + ) + ) + fsm.act("ACK", + self.wishbone.ack.eq(1), + NextState("WRITE-READ") + ) -- 2.30.2