From 142a722ce473a53f589e0f05d7eaa66b77b0ac27 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 12 Sep 2019 09:04:02 +1000 Subject: [PATCH] Remove names from end record statements These are optional, and vhdlpp from iverilog barfs on them. Signed-off-by: Anton Blanchard --- fpga/clk_gen_mcmm.vhd | 2 +- fpga/clk_gen_plle2.vhd | 2 +- wishbone_types.vhdl | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/fpga/clk_gen_mcmm.vhd b/fpga/clk_gen_mcmm.vhd index b76995a..206b02a 100644 --- a/fpga/clk_gen_mcmm.vhd +++ b/fpga/clk_gen_mcmm.vhd @@ -22,7 +22,7 @@ architecture rtl of clock_generator is clkfbout_mult : real range 2.0 to 64.0; clkout_divide : real range 1.0 to 128.0; divclk_divide : integer range 1 to 106; - end record pll_settings_t; + end record; function gen_pll_settings ( constant freq_hz : positive) diff --git a/fpga/clk_gen_plle2.vhd b/fpga/clk_gen_plle2.vhd index e2c761c..f82cb53 100644 --- a/fpga/clk_gen_plle2.vhd +++ b/fpga/clk_gen_plle2.vhd @@ -23,7 +23,7 @@ architecture rtl of clock_generator is clkfbout_mult : integer range 2 to 64; clkout_divide : integer range 1 to 128; divclk_divide : integer range 1 to 56; - end record pll_settings_t; + end record; function gen_pll_settings ( constant freq_hz : positive) diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl index 24c46d7..6055d9c 100644 --- a/wishbone_types.vhdl +++ b/wishbone_types.vhdl @@ -15,13 +15,13 @@ package wishbone_types is stb : std_ulogic; sel : std_ulogic_vector(7 downto 0); we : std_ulogic; - end record wishbone_master_out; + end record; constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0')); type wishbone_slave_out is record dat : wishbone_data_type; ack : std_ulogic; - end record wishbone_slave_out; + end record; constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0')); end package wishbone_types; -- 2.30.2