From 1464aba03659adec485de985b4b3ebcfc02ba487 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jul 2019 10:06:29 +0100
Subject: [PATCH] big convert g/s/r mid --> muxid

---
 src/ieee754/add/inputgroup.py            |  6 +--
 src/ieee754/add/test_inputgroup.py       | 40 ++++++++--------
 src/ieee754/fpadd/add0.py                |  2 +-
 src/ieee754/fpadd/align.py               |  2 +-
 src/ieee754/fpadd/statemachine.py        |  6 +--
 src/ieee754/fpcommon/denorm.py           |  2 +-
 src/ieee754/fpcommon/getop.py            | 14 +++---
 src/ieee754/fpcommon/pack.py             |  2 +-
 src/ieee754/fpcommon/postcalc.py         |  2 +-
 src/ieee754/fpcommon/postnormalise.py    |  2 +-
 src/ieee754/fpcommon/roundz.py           |  2 +-
 src/ieee754/fpcommon/test/fpmux.py       | 43 ++++++++---------
 src/ieee754/fpdiv/div0.py                |  2 +-
 src/ieee754/fpmul/mul0.py                |  2 +-
 src/nmutil/multipipe.py                  | 16 +++----
 src/nmutil/test/test_inout_mux_pipe.py   | 60 ++++++++++++------------
 src/nmutil/test/test_outmux_pipe.py      | 32 ++++++-------
 src/nmutil/test/test_prioritymux_pipe.py | 54 ++++++++++-----------
 18 files changed, 145 insertions(+), 144 deletions(-)

diff --git a/src/ieee754/add/inputgroup.py b/src/ieee754/add/inputgroup.py
index 9322c8a1..6069817e 100644
--- a/src/ieee754/add/inputgroup.py
+++ b/src/ieee754/add/inputgroup.py
@@ -63,7 +63,7 @@ class InputGroup:
         self.num_rows = num_rows
         self.mmax = int(log(self.num_rows) / log(2))
         self.rs = []
-        self.mid = Signal(self.mmax, reset_less=True) # multiplex id
+        self.muxid = Signal(self.mmax, reset_less=True) # multiplex id
         for i in range(num_rows):
             self.rs.append(FPGetSyncOpsMod(width, num_ops))
         self.rs = Array(self.rs)
@@ -92,7 +92,7 @@ class InputGroup:
         # encoder active: ack relevant input, record MID, pass output
         with m.If(out_en):
             rs = self.rs[pe.o]
-            m.d.sync += self.mid.eq(pe.o)
+            m.d.sync += self.muxid.eq(pe.o)
             m.d.sync += rs.ack.eq(0)
             m.d.sync += self.out_op.stb.eq(0)
             for j in range(self.num_ops):
@@ -110,6 +110,6 @@ class InputGroup:
         for i in range(self.num_rows):
             inop = self.rs[i]
             res += inop.in_op + [inop.stb]
-        return self.out_op.ports() + res + [self.mid]
+        return self.out_op.ports() + res + [self.muxid]
 
 
diff --git a/src/ieee754/add/test_inputgroup.py b/src/ieee754/add/test_inputgroup.py
index 09a72e17..96de216f 100644
--- a/src/ieee754/add/test_inputgroup.py
+++ b/src/ieee754/add/test_inputgroup.py
@@ -43,8 +43,8 @@ def testbench(dut):
     # output strobe should be active, MID should be 0 until "ack" is set...
     out_stb = yield dut.out_op.stb
     assert out_stb == 1
-    out_mid = yield dut.mid
-    assert out_mid == 0
+    out_muxid = yield dut.muxid
+    assert out_muxid == 0
 
     # ... and output should not yet be passed through either
     op0 = yield dut.out_op.v[0]
@@ -72,8 +72,8 @@ def testbench(dut):
     op0 = yield dut.out_op.v[0]
     op1 = yield dut.out_op.v[1]
     assert op0 == 3 and op1 == 4, "op0 %d op1 %d" % (op0, op1)
-    out_mid = yield dut.mid
-    assert out_mid == 2
+    out_muxid = yield dut.muxid
+    assert out_muxid == 2
 
     # set row 0 and 3 input
     yield dut.rs[0].in_op[0].eq(9)
@@ -88,15 +88,15 @@ def testbench(dut):
     yield
     yield dut.rs[0].stb.eq(0) # clear row 1 strobe
     yield
-    out_mid = yield dut.mid
-    assert out_mid == 0, "out mid %d" % out_mid
+    out_muxid = yield dut.muxid
+    assert out_muxid == 0, "out muxid %d" % out_muxid
 
     yield
     yield dut.rs[3].stb.eq(0) # clear row 1 strobe
     yield dut.out_op.ack.eq(0) # clear ack on output
     yield
-    out_mid = yield dut.mid
-    assert out_mid == 3, "out mid %d" % out_mid
+    out_muxid = yield dut.muxid
+    assert out_muxid == 3, "out muxid %d" % out_muxid
 
 
 class InputTest:
@@ -105,17 +105,17 @@ class InputTest:
         self.di = {}
         self.do = {}
         self.tlen = 10
-        for mid in range(dut.num_rows):
-            self.di[mid] = {}
-            self.do[mid] = {}
+        for muxid in range(dut.num_rows):
+            self.di[muxid] = {}
+            self.do[muxid] = {}
             for i in range(self.tlen):
-                self.di[mid][i] = randint(0, 100)
-                self.do[mid][i] = self.di[mid][i]
+                self.di[muxid][i] = randint(0, 100)
+                self.do[muxid][i] = self.di[muxid][i]
 
-    def send(self, mid):
+    def send(self, muxid):
         for i in range(self.tlen):
-            op2 = self.di[mid][i]
-            rs = dut.rs[mid]
+            op2 = self.di[muxid][i]
+            rs = dut.rs[muxid]
             ack = yield rs.ack
             while not ack:
                 yield
@@ -146,14 +146,14 @@ class InputTest:
             while stb:
                 yield
                 stb = yield dut.out_op.stb
-            mid = yield dut.mid
+            muxid = yield dut.muxid
             out_i = yield dut.out_op.v[0]
             out_v = yield dut.out_op.v[1]
 
             # see if this output has occurred already, delete it if it has
-            assert out_i in self.do[mid]
-            assert self.do[mid][out_i] == out_v
-            del self.do[mid][out_i]
+            assert out_i in self.do[muxid]
+            assert self.do[muxid][out_i] == out_v
+            del self.do[muxid][out_i]
 
             # check if there's any more outputs
             zerolen = True
diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index b487b0dd..d5336b3c 100644
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -19,7 +19,7 @@ class FPAddStage0Data:
         self.oz = Signal(width, reset_less=True)
         self.tot = Signal(self.z.m_width + 4, reset_less=True)
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py
index 171365ef..b357e309 100644
--- a/src/ieee754/fpadd/align.py
+++ b/src/ieee754/fpadd/align.py
@@ -22,7 +22,7 @@ class FPNumIn2Ops:
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 0ca7ce7a..decbc3d4 100644
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -33,14 +33,14 @@ class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOpOut(width)
         self.z.data_o = Signal(width)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def __iter__(self):
         yield self.z
-        yield self.mid
+        yield self.muxid
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+        return [self.z.eq(i.z), self.muxid.eq(i.mid)]
 
     def ports(self):
         return list(self)
diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index f6b26c2a..5c20e535 100644
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -25,7 +25,7 @@ class FPSCData:
         self.oz = Signal(width, reset_less=True)   # "finished" (bypass) result
         self.out_do_z = Signal(reset_less=True)    # "bypass" enabled
         self.ctx = FPBaseData(width, pspec) 
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def __iter__(self):
         yield from self.a
diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index 17a8334b..5ca46bfd 100644
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -73,13 +73,13 @@ class FPNumBase2Ops:
     def __init__(self, width, id_wid, m_extra=True):
         self.a = FPNumBase(width, m_extra)
         self.b = FPNumBase(width, m_extra)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+        return [self.a.eq(i.a), self.b.eq(i.b), self.muxid.eq(i.muxid)]
 
     def ports(self):
-        return [self.a, self.b, self.mid]
+        return [self.a, self.b, self.muxid]
 
 
 class FPBaseData:
@@ -89,17 +89,17 @@ class FPBaseData:
         print (pspec)
         self.id_wid = pspec['id_wid']
         self.op_wid = pspec.get('op_wid', 0)
-        self.mid = Signal(self.id_wid, reset_less=True)   # RS multiplex ID
+        self.muxid = Signal(self.id_wid, reset_less=True)   # RS multiplex ID
         self.op = Signal(self.op_wid, reset_less=True)
 
     def eq(self, i):
-        ret = [self.mid.eq(i.mid)]
+        ret = [self.muxid.eq(i.muxid)]
         if self.op_wid:
             ret.append(self.op.eq(i.op))
         return ret
 
     def __iter__(self):
-        yield self.mid
+        yield self.muxid
         if self.op_wid:
             yield self.op
 
@@ -118,7 +118,7 @@ class FPADDBaseData:
             operand = Signal(width, name=name)
             setattr(self, name, operand)
             ops.append(operand)
-        self.mid = self.ctx.mid # make muxid available here: complicated
+        self.muxid = self.ctx.muxid # make muxid available here: complicated
         self.ops = ops
 
     def eq(self, i):
diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index 5df5ea7c..37ab1eca 100644
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -18,7 +18,7 @@ class FPPackData(Object):
         Object.__init__(self)
         self.z = Signal(width, reset_less=True)    # result
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
 class FPPackMod(Elaboratable):
 
diff --git a/src/ieee754/fpcommon/postcalc.py b/src/ieee754/fpcommon/postcalc.py
index b815f8cf..24475d38 100644
--- a/src/ieee754/fpcommon/postcalc.py
+++ b/src/ieee754/fpcommon/postcalc.py
@@ -14,7 +14,7 @@ class FPAddStage1Data:
         self.oz = Signal(width, reset_less=True)
         self.of = Overflow()
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def __iter__(self):
         yield from self.z
diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py
index 0f593865..ce7aad16 100644
--- a/src/ieee754/fpcommon/postnormalise.py
+++ b/src/ieee754/fpcommon/postnormalise.py
@@ -22,7 +22,7 @@ class FPNorm1Data:
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def eq(self, i):
         ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index a0b56868..ceec0c46 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -16,7 +16,7 @@ class FPRoundData:
     def __init__(self, width, pspec):
         self.z = FPNumBaseRecord(width, False)
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
         # pipeline bypass [data comes from specialcases]
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 01832ec4..239c822d 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -19,9 +19,9 @@ class InputTest:
         self.do = {}
         self.tlen = 10
         self.width = width
-        for mid in range(dut.num_rows):
-            self.di[mid] = {}
-            self.do[mid] = []
+        for muxid in range(dut.num_rows):
+            self.di[muxid] = {}
+            self.do[muxid] = []
             for i in range(self.tlen):
                 op1 = randint(0, (1<<self.width)-1)
                 op2 = randint(0, (1<<self.width)-1)
@@ -36,17 +36,17 @@ class InputTest:
                 #op1 = 0x40900000
                 #op2 = 0x40200000
                 res = self.fpop(self.fpkls(op1), self.fpkls(op2))
-                self.di[mid][i] = (op1, op2)
-                self.do[mid].append(res.bits)
+                self.di[muxid][i] = (op1, op2)
+                self.do[muxid].append(res.bits)
 
-    def send(self, mid):
+    def send(self, muxid):
         for i in range(self.tlen):
-            op1, op2 = self.di[mid][i]
-            rs = self.dut.p[mid]
+            op1, op2 = self.di[muxid][i]
+            rs = self.dut.p[muxid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.a.eq(op1)
             yield rs.data_i.b.eq(op2)
-            yield rs.data_i.mid.eq(mid)
+            yield rs.data_i.muxid.eq(muxid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
@@ -56,7 +56,7 @@ class InputTest:
             fop1 = self.fpkls(op1)
             fop2 = self.fpkls(op2)
             res = self.fpop(fop1, fop2)
-            print ("send", mid, i, hex(op1), hex(op2), hex(res.bits),
+            print ("send", muxid, i, hex(op1), hex(op2), hex(res.bits),
                            fop1, fop2, res)
 
             yield rs.valid_i.eq(0)
@@ -67,7 +67,7 @@ class InputTest:
         yield rs.valid_i.eq(0)
         yield
 
-        print ("send ended", mid)
+        print ("send ended", muxid)
 
         ## wait random period of time before queueing another value
         #for i in range(randint(0, 3)):
@@ -79,14 +79,14 @@ class InputTest:
         #else:
         #    send = randint(0, send_range) != 0
 
-    def rcv(self, mid):
+    def rcv(self, muxid):
         while True:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
             #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
-            n = self.dut.n[mid]
+            n = self.dut.n[muxid]
             yield n.ready_i.eq(1)
             yield
             o_n_valid = yield n.valid_o
@@ -94,23 +94,24 @@ class InputTest:
             if not o_n_valid or not i_n_ready:
                 continue
 
-            out_mid = yield n.data_o.mid
+            out_muxid = yield n.data_o.muxid
             out_z = yield n.data_o.z
 
             out_i = 0
 
-            print ("recv", out_mid, hex(out_z), "expected",
-                        hex(self.do[mid][out_i] ))
+            print ("recv", out_muxid, hex(out_z), "expected",
+                        hex(self.do[muxid][out_i] ))
 
             # see if this output has occurred already, delete it if it has
-            assert mid == out_mid, "out_mid %d not correct %d" % (out_mid, mid)
-            assert self.do[mid][out_i] == out_z
-            del self.do[mid][out_i]
+            assert muxid == out_muxid, "out_muxid %d not correct %d" % \
+                                       (out_muxid, muxid)
+            assert self.do[muxid][out_i] == out_z
+            del self.do[muxid][out_i]
 
             # check if there's any more outputs
-            if len(self.do[mid]) == 0:
+            if len(self.do[muxid]) == 0:
                 break
-        print ("recv ended", mid)
+        print ("recv ended", muxid)
 
 
 def runfp(dut, width, name, fpkls, fpop):
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 330d5af5..2ad8bcda 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -21,7 +21,7 @@ class FPDivStage0Data:
         self.of = Overflow()
 
         self.ctx = FPBaseData(width, pspec) # context: muxid, operator etc.
-        self.mid = self.ctx.mid             # annoying. complicated.
+        self.muxid = self.ctx.muxid             # annoying. complicated.
 
         # TODO: here is where Q and R would be put, and passed
         # down to Stage1 processing.
diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 59067856..99893efd 100644
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -20,7 +20,7 @@ class FPMulStage0Data:
         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         self.product = Signal(mw, reset_less=True)
         self.ctx = FPBaseData(width, pspec)
-        self.mid = self.ctx.mid
+        self.muxid = self.ctx.muxid
 
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py
index 82e3b8ae..3fc58e79 100644
--- a/src/nmutil/multipipe.py
+++ b/src/nmutil/multipipe.py
@@ -186,7 +186,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
             self.stage.setup(m, r_data)
 
         # multiplexer id taken from n_mux
-        mid = self.n_mux.m_id
+        muxid = self.n_mux.m_id
         print ("self.n_mux", self.n_mux)
         print ("self.n_mux.m_id", self.n_mux.m_id)
 
@@ -200,13 +200,13 @@ class CombMultiOutPipeline(MultiOutControlBase):
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
             m.d.comb += self.n[i].valid_o.eq(0)
-        data_valid = self.n[mid].valid_o
-        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
+        data_valid = self.n[muxid].valid_o
+        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[muxid].ready_i)
         m.d.comb += data_valid.eq(p_valid_i | \
-                                    (~self.n[mid].ready_i & data_valid))
+                                    (~self.n[muxid].ready_i & data_valid))
         with m.If(pv):
             m.d.comb += eq(r_data, self.p.data_i)
-        m.d.comb += eq(self.n[mid].data_o, self.process(r_data))
+        m.d.comb += eq(self.n[muxid].data_o, self.process(r_data))
 
         return m
 
@@ -304,9 +304,9 @@ class CombMuxOutPipe(CombMultiOutPipeline):
         # HACK: stage is also the n-way multiplexer
         CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
 
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        print ("combmuxout", self.p.data_i.mid)
-        stage.m_id = self.p.data_i.mid
+        # HACK: n-mux is also the stage... so set the muxid equal to input muxid
+        print ("combmuxout", self.p.data_i.muxid)
+        stage.m_id = self.p.data_i.muxid
 
 
 
diff --git a/src/nmutil/test/test_inout_mux_pipe.py b/src/nmutil/test/test_inout_mux_pipe.py
index fe743551..a1844274 100644
--- a/src/nmutil/test/test_inout_mux_pipe.py
+++ b/src/nmutil/test/test_inout_mux_pipe.py
@@ -19,7 +19,7 @@ from nmutil.singlepipe import SimpleHandshake, RecordObject, Object
 class PassData2(RecordObject):
     def __init__(self):
         RecordObject.__init__(self)
-        self.mid = Signal(2, reset_less=True)
+        self.muxid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
@@ -27,7 +27,7 @@ class PassData2(RecordObject):
 class PassData(Object):
     def __init__(self):
         Object.__init__(self)
-        self.mid = Signal(2, reset_less=True)
+        self.muxid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
@@ -55,28 +55,28 @@ class InputTest:
         self.di = {}
         self.do = {}
         self.tlen = 100
-        for mid in range(dut.num_rows):
-            self.di[mid] = {}
-            self.do[mid] = {}
+        for muxid in range(dut.num_rows):
+            self.di[muxid] = {}
+            self.do[muxid] = {}
             for i in range(self.tlen):
-                self.di[mid][i] = randint(0, 255) + (mid<<8)
-                self.do[mid][i] = self.di[mid][i]
+                self.di[muxid][i] = randint(0, 255) + (muxid<<8)
+                self.do[muxid][i] = self.di[muxid][i]
 
-    def send(self, mid):
+    def send(self, muxid):
         for i in range(self.tlen):
-            op2 = self.di[mid][i]
-            rs = self.dut.p[mid]
+            op2 = self.di[muxid][i]
+            rs = self.dut.p[muxid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.data.eq(op2)
             yield rs.data_i.idx.eq(i)
-            yield rs.data_i.mid.eq(mid)
+            yield rs.data_i.muxid.eq(muxid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
                 o_p_ready = yield rs.ready_o
 
-            print ("send", mid, i, hex(op2))
+            print ("send", muxid, i, hex(op2))
 
             yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
@@ -86,7 +86,7 @@ class InputTest:
         yield rs.valid_i.eq(0)
         yield
 
-        print ("send ended", mid)
+        print ("send ended", muxid)
 
         ## wait random period of time before queueing another value
         #for i in range(randint(0, 3)):
@@ -98,14 +98,14 @@ class InputTest:
         #else:
         #    send = randint(0, send_range) != 0
 
-    def rcv(self, mid):
+    def rcv(self, muxid):
         while True:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
             #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
-            n = self.dut.n[mid]
+            n = self.dut.n[muxid]
             yield n.ready_i.eq(1)
             yield
             o_n_valid = yield n.valid_o
@@ -113,23 +113,23 @@ class InputTest:
             if not o_n_valid or not i_n_ready:
                 continue
 
-            out_mid = yield n.data_o.mid
+            out_muxid = yield n.data_o.muxid
             out_i = yield n.data_o.idx
             out_v = yield n.data_o.data
 
-            print ("recv", out_mid, out_i, hex(out_v))
+            print ("recv", out_muxid, out_i, hex(out_v))
 
             # see if this output has occurred already, delete it if it has
-            assert mid == out_mid, "out_mid %d not correct %d" % (out_mid, mid)
-            assert out_i in self.do[mid], "out_i %d not in array %s" % \
-                                          (out_i, repr(self.do[mid]))
-            assert self.do[mid][out_i] == out_v # pass-through data
-            del self.do[mid][out_i]
+            assert muxid == out_muxid, "out_muxid %d not correct %d" % (out_muxid, muxid)
+            assert out_i in self.do[muxid], "out_i %d not in array %s" % \
+                                          (out_i, repr(self.do[muxid]))
+            assert self.do[muxid][out_i] == out_v # pass-through data
+            del self.do[muxid][out_i]
 
             # check if there's any more outputs
-            if len(self.do[mid]) == 0:
+            if len(self.do[muxid]) == 0:
                 break
-        print ("recv ended", mid)
+        print ("recv ended", muxid)
 
 
 class TestPriorityMuxPipe(PriorityCombMuxInPipe):
@@ -147,26 +147,26 @@ class OutputTest:
         self.tlen = 100
         for i in range(self.tlen * dut.num_rows):
             if i < dut.num_rows:
-                mid = i
+                muxid = i
             else:
-                mid = randint(0, dut.num_rows-1)
-            data = randint(0, 255) + (mid<<8)
+                muxid = randint(0, dut.num_rows-1)
+            data = randint(0, 255) + (muxid<<8)
 
     def send(self):
         for i in range(self.tlen * dut.num_rows):
             op2 = self.di[i][0]
-            mid = self.di[i][1]
+            muxid = self.di[i][1]
             rs = dut.p
             yield rs.valid_i.eq(1)
             yield rs.data_i.data.eq(op2)
-            yield rs.data_i.mid.eq(mid)
+            yield rs.data_i.muxid.eq(muxid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
                 o_p_ready = yield rs.ready_o
 
-            print ("send", mid, i, hex(op2))
+            print ("send", muxid, i, hex(op2))
 
             yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
diff --git a/src/nmutil/test/test_outmux_pipe.py b/src/nmutil/test/test_outmux_pipe.py
index 9daffac9..842b130b 100644
--- a/src/nmutil/test/test_outmux_pipe.py
+++ b/src/nmutil/test/test_outmux_pipe.py
@@ -11,7 +11,7 @@ from nmutil.singlepipe import SimpleHandshake, PassThroughHandshake, RecordObjec
 class PassInData(RecordObject):
     def __init__(self):
         RecordObject.__init__(self)
-        self.mid = Signal(2, reset_less=True)
+        self.muxid = Signal(2, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
 
@@ -51,30 +51,30 @@ class OutputTest:
         self.tlen = 10
         for i in range(self.tlen * dut.num_rows):
             if i < dut.num_rows:
-                mid = i
+                muxid = i
             else:
-                mid = randint(0, dut.num_rows-1)
-            data = randint(0, 255) + (mid<<8)
-            if mid not in self.do:
-                self.do[mid] = []
-            self.di.append((data, mid))
-            self.do[mid].append(data)
+                muxid = randint(0, dut.num_rows-1)
+            data = randint(0, 255) + (muxid<<8)
+            if muxid not in self.do:
+                self.do[muxid] = []
+            self.di.append((data, muxid))
+            self.do[muxid].append(data)
 
     def send(self):
         for i in range(self.tlen * self.dut.num_rows):
             op2 = self.di[i][0]
-            mid = self.di[i][1]
+            muxid = self.di[i][1]
             rs = self.dut.p
             yield rs.valid_i.eq(1)
             yield rs.data_i.data.eq(op2)
-            yield rs.data_i.mid.eq(mid)
+            yield rs.data_i.muxid.eq(muxid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
                 o_p_ready = yield rs.ready_o
 
-            print ("send", mid, i, hex(op2))
+            print ("send", muxid, i, hex(op2))
 
             yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
@@ -83,14 +83,14 @@ class OutputTest:
 
         yield rs.valid_i.eq(0)
 
-    def rcv(self, mid):
+    def rcv(self, muxid):
         out_i = 0
         count = 0
         stall_range = randint(0, 3)
-        while out_i != len(self.do[mid]):
+        while out_i != len(self.do[muxid]):
             count += 1
             assert count != 2000, "timeout: too long"
-            n = self.dut.n[mid]
+            n = self.dut.n[muxid]
             yield n.ready_i.eq(1)
             yield
             o_n_valid = yield n.valid_o
@@ -100,9 +100,9 @@ class OutputTest:
 
             out_v = yield n.data_o
 
-            print ("recv", mid, out_i, hex(out_v))
+            print ("recv", muxid, out_i, hex(out_v))
 
-            assert self.do[mid][out_i] == out_v # pass-through data
+            assert self.do[muxid][out_i] == out_v # pass-through data
 
             out_i += 1
 
diff --git a/src/nmutil/test/test_prioritymux_pipe.py b/src/nmutil/test/test_prioritymux_pipe.py
index c80a179e..1b2f4e45 100644
--- a/src/nmutil/test/test_prioritymux_pipe.py
+++ b/src/nmutil/test/test_prioritymux_pipe.py
@@ -10,15 +10,15 @@ from nmutil.multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
 
 class PassData:
     def __init__(self):
-        self.mid = Signal(2, reset_less=True)
+        self.muxid = Signal(2, reset_less=True)
         self.idx = Signal(6, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
     def eq(self, i):
-        return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
+        return [self.muxid.eq(i.muxid), self.idx.eq(i.idx), self.data.eq(i.data)]
 
     def ports(self):
-        return [self.mid, self.idx, self.data]
+        return [self.muxid, self.idx, self.data]
 
 
 def tbench(dut):
@@ -58,8 +58,8 @@ def tbench(dut):
     # output strobe should be active, MID should be 0 until "ack" is set...
     out_stb = yield dut.out_op.stb
     assert out_stb == 1
-    out_mid = yield dut.mid
-    assert out_mid == 0
+    out_muxid = yield dut.muxid
+    assert out_muxid == 0
 
     # ... and output should not yet be passed through either
     op0 = yield dut.out_op.v[0]
@@ -87,8 +87,8 @@ def tbench(dut):
     op0 = yield dut.out_op.v[0]
     op1 = yield dut.out_op.v[1]
     assert op0 == 3 and op1 == 4, "op0 %d op1 %d" % (op0, op1)
-    out_mid = yield dut.mid
-    assert out_mid == 2
+    out_muxid = yield dut.muxid
+    assert out_muxid == 2
 
     # set row 0 and 3 input
     yield dut.rs[0].in_op[0].eq(9)
@@ -103,15 +103,15 @@ def tbench(dut):
     yield
     yield dut.rs[0].stb.eq(0) # clear row 1 strobe
     yield
-    out_mid = yield dut.mid
-    assert out_mid == 0, "out mid %d" % out_mid
+    out_muxid = yield dut.muxid
+    assert out_muxid == 0, "out muxid %d" % out_muxid
 
     yield
     yield dut.rs[3].stb.eq(0) # clear row 1 strobe
     yield dut.out_op.ack.eq(0) # clear ack on output
     yield
-    out_mid = yield dut.mid
-    assert out_mid == 3, "out mid %d" % out_mid
+    out_muxid = yield dut.muxid
+    assert out_muxid == 3, "out muxid %d" % out_muxid
 
 
 class InputTest:
@@ -120,28 +120,28 @@ class InputTest:
         self.di = {}
         self.do = {}
         self.tlen = 10
-        for mid in range(dut.num_rows):
-            self.di[mid] = {}
-            self.do[mid] = {}
+        for muxid in range(dut.num_rows):
+            self.di[muxid] = {}
+            self.do[muxid] = {}
             for i in range(self.tlen):
-                self.di[mid][i] = randint(0, 100) + (mid<<8)
-                self.do[mid][i] = self.di[mid][i]
+                self.di[muxid][i] = randint(0, 100) + (muxid<<8)
+                self.do[muxid][i] = self.di[muxid][i]
 
-    def send(self, mid):
+    def send(self, muxid):
         for i in range(self.tlen):
-            op2 = self.di[mid][i]
-            rs = self.dut.p[mid]
+            op2 = self.di[muxid][i]
+            rs = self.dut.p[muxid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.data.eq(op2)
             yield rs.data_i.idx.eq(i)
-            yield rs.data_i.mid.eq(mid)
+            yield rs.data_i.muxid.eq(muxid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
                 yield
                 o_p_ready = yield rs.ready_o
 
-            print ("send", mid, i, hex(op2))
+            print ("send", muxid, i, hex(op2))
 
             yield rs.valid_i.eq(0)
             # wait random period of time before queueing another value
@@ -174,17 +174,17 @@ class InputTest:
             if not o_n_valid or not i_n_ready:
                 continue
 
-            mid = yield n.data_o.mid
+            muxid = yield n.data_o.muxid
             out_i = yield n.data_o.idx
             out_v = yield n.data_o.data
 
-            print ("recv", mid, out_i, hex(out_v))
+            print ("recv", muxid, out_i, hex(out_v))
 
             # see if this output has occurred already, delete it if it has
-            assert out_i in self.do[mid], "out_i %d not in array %s" % \
-                                          (out_i, repr(self.do[mid]))
-            assert self.do[mid][out_i] == out_v # pass-through data
-            del self.do[mid][out_i]
+            assert out_i in self.do[muxid], "out_i %d not in array %s" % \
+                                          (out_i, repr(self.do[muxid]))
+            assert self.do[muxid][out_i] == out_v # pass-through data
+            del self.do[muxid][out_i]
 
             # check if there's any more outputs
             zerolen = True
-- 
2.30.2