From 149364f7ad265599f9a0ec2dbfe42fbdcfbd705e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 20:58:26 +0100 Subject: [PATCH] update comments --- src/soc/fu/cr/main_stage.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 7240ebe5..607579d1 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -47,11 +47,12 @@ class CRMainStage(PipeModBase): mask = Signal(32, reset_less=True) comb += mask.eq(Cat(*[Repl(FXM[i], 4) for i in range(8)])) - # Generate array of bits for cr_a and cr_b + # Generate array of bits for cr_a, cr_b and cr_c cr_a_arr = Array([cr_a[i] for i in range(4)]) cr_b_arr = Array([cr_b[i] for i in range(4)]) cr_o_arr = Array([cr_o[i] for i in range(4)]) + # this may have one bit be modified by OP_CROP comb += cr_o.eq(cr_c) with m.Switch(op.insn_type): -- 2.30.2