From 14e7d55ec05b36116874a9324e965c7b3c5c8ceb Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 25 May 2022 10:23:49 +0100 Subject: [PATCH] --- openpower/sv/int_fp_mv.mdwn | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 3d454b63f..7f0d9d7a4 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -221,26 +221,13 @@ change all [GPR to FPR conversion instructions](#GPR-to-FPR-conversions) to instead write `+0.0` if `RA` is register `0`, at least allowing clearing FPRs. -| 0-5 | 6-10 | 11-25 | 26-30 | 31 | -|--------|------|-------|-------|-----| -| Major | FRT | FI | XO | FI0 | +`fmvis` fits well with DX-Form: -The above fits reasonably well with Minor 19 and follows the -pattern shown by `addpcis`, which uses an entire column of Minor 19 -XO. 15 bits of FI fit into bits 11 to 25, -the top bit FI0 (MSB0 numbered 0) makes 16. +| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form +|--------|------|-------|-------|-------|-----|-----| +| Major | FRT | d1 | d0 | XO | d2 | DX-Form | - bf16 = FI0 || FI - fp32 = bf16 || [0]*16 - FRT = Single_to_Double(fp32) - -Also worth noting, `fmvis` fits well with DX-Form: - -| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | -|--------|------|-------|-------|-------|-----| -| Major | FRT | d0 | d1 | XO | d2 | - - bf16 = d2 || d1 || d0 + bf16 = d0 || d1 || d2 fp32 = bf16 || [0]*16 FRT = Single_to_Double(fp32) -- 2.30.2