From 14f45d6b9fc14b4dcfb86464cb61536de48023cc Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Wed, 17 Mar 1999 10:33:17 -0800 Subject: [PATCH] sparc.h (TARGET_SWITCHES, [...]): Add descriptions. * config/sparc/sparc.h (TARGET_SWITCHES, TARGET_OPTIONS): Add descriptions. * config/sparc/sp64-elf.h (SUBTARGET_SWITCHES): Likewise. * config/sparc/splet.h (SUBTARGET_SWITCHES): Likewise. From-SVN: r25827 --- gcc/ChangeLog | 7 ++++ gcc/config/sparc/sp64-elf.h | 4 +- gcc/config/sparc/sparc.h | 80 ++++++++++++++++++------------------- gcc/config/sparc/splet.h | 12 +++--- 4 files changed, 55 insertions(+), 48 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3d8f5fe8c44..17611fcbdc3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +Wed Mar 17 18:20:24 1999 David S. Miller + + * config/sparc/sparc.h (TARGET_SWITCHES, TARGET_OPTIONS): + Add descriptions. + * config/sparc/sp64-elf.h (SUBTARGET_SWITCHES): Likewise. + * config/sparc/splet.h (SUBTARGET_SWITCHES): Likewise. + Wed Mar 17 14:51:19 1999 Richard Henderson * alpha.h (HARD_REGNO_MODE_OK): Allow only 4 and 8 byte unit modes diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h index a1e4ef0c252..4fd81c55c47 100644 --- a/gcc/config/sparc/sp64-elf.h +++ b/gcc/config/sparc/sp64-elf.h @@ -80,8 +80,8 @@ crtbegin.o%s \ /* V9 chips can handle either endianness. */ #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ -{"big-endian", -MASK_LITTLE_ENDIAN}, \ -{"little-endian", MASK_LITTLE_ENDIAN}, +{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \ +{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, #undef BYTES_BIG_ENDIAN #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 2954539d306..c25d0fd6339 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -569,42 +569,42 @@ extern int target_flags; An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ - { {"fpu", MASK_FPU | MASK_FPU_SET}, \ - {"no-fpu", -MASK_FPU}, \ - {"no-fpu", MASK_FPU_SET}, \ - {"hard-float", MASK_FPU | MASK_FPU_SET}, \ - {"soft-float", -MASK_FPU}, \ - {"soft-float", MASK_FPU_SET}, \ - {"epilogue", MASK_EPILOGUE}, \ - {"no-epilogue", -MASK_EPILOGUE}, \ - {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ - {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ - {"impure-text", MASK_IMPURE_TEXT}, \ - {"no-impure-text", -MASK_IMPURE_TEXT}, \ - {"flat", MASK_FLAT}, \ - {"no-flat", -MASK_FLAT}, \ - {"app-regs", MASK_APP_REGS}, \ - {"no-app-regs", -MASK_APP_REGS}, \ - {"hard-quad-float", MASK_HARD_QUAD}, \ - {"soft-quad-float", -MASK_HARD_QUAD}, \ - {"v8plus", MASK_V8PLUS}, \ - {"no-v8plus", -MASK_V8PLUS}, \ - {"vis", MASK_VIS}, \ - {"no-vis", -MASK_VIS}, \ + { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ + {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \ + {"no-fpu", MASK_FPU_SET, "Do not use hardware fp" }, \ + {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ + {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \ + {"soft-float", MASK_FPU_SET, "Do not use hardware fp" }, \ + {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \ + {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \ + {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\ + {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \ + {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \ + {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \ + {"flat", MASK_FLAT, "Use flat register window model" }, \ + {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \ + {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \ + {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \ + {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \ + {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \ + {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \ + {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \ + {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \ + {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \ /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ - {"cypress", 0}, \ - {"sparclite", 0}, \ - {"f930", 0}, \ - {"f934", 0}, \ - {"v8", 0}, \ - {"supersparc", 0}, \ + {"cypress", 0, "Optimize for Cypress processors" }, \ + {"sparclite", 0, "Optimize for SparcLite processors" }, \ + {"f930", 0, "Optimize for F930 processors" }, \ + {"f934", 0, "Optimize for F934 processors" }, \ + {"v8", 0, "Use V8 Sparc ISA" }, \ + {"supersparc", 0, "Optimize for SuperSparc processors" }, \ /* End of deprecated options. */ \ - {"ptr64", MASK_PTR64}, \ - {"ptr32", -MASK_PTR64}, \ - {"32", -MASK_64BIT}, \ - {"64", MASK_64BIT}, \ - {"stack-bias", MASK_STACK_BIAS}, \ - {"no-stack-bias", -MASK_STACK_BIAS}, \ + {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \ + {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \ + {"32", -MASK_64BIT, "Use 32-bit ABI" }, \ + {"64", MASK_64BIT, "Use 64-bit ABI" }, \ + {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \ + {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \ SUBTARGET_SWITCHES \ { "", TARGET_DEFAULT}} @@ -660,12 +660,12 @@ extern enum processor_type sparc_cpu; #define TARGET_OPTIONS \ { \ - { "cpu=", &sparc_select[1].string }, \ - { "tune=", &sparc_select[2].string }, \ - { "cmodel=", &sparc_cmodel_string }, \ - { "align-loops=", &sparc_align_loops_string }, \ - { "align-jumps=", &sparc_align_jumps_string }, \ - { "align-functions=", &sparc_align_funcs_string }, \ + { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \ + { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \ + { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \ + { "align-loops=", &sparc_align_loops_string, "Loop code aligned to this power of 2" }, \ + { "align-jumps=", &sparc_align_jumps_string, "Jump targets are aligned to this power of 2" }, \ + { "align-functions=", &sparc_align_funcs_string, "Function starts are aligned to this power of 2" }, \ SUBTARGET_OPTIONS \ } diff --git a/gcc/config/sparc/splet.h b/gcc/config/sparc/splet.h index 50dbb585e69..d924e708996 100644 --- a/gcc/config/sparc/splet.h +++ b/gcc/config/sparc/splet.h @@ -29,12 +29,12 @@ Boston, MA 02111-1307, USA. */ /* -mlive-g0 is only supported on the sparclet. */ #undef SUBTARGET_SWITCHES #define SUBTARGET_SWITCHES \ -{"big-endian", -MASK_LITTLE_ENDIAN}, \ -{"little-endian", MASK_LITTLE_ENDIAN}, \ -{"live-g0", MASK_LIVE_G0}, \ -{"no-live-g0", -MASK_LIVE_G0}, \ -{"broken-saverestore", MASK_BROKEN_SAVERESTORE}, \ -{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE}, +{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \ +{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, \ +{"live-g0", MASK_LIVE_G0, "Use g0 as a normal register" }, \ +{"no-live-g0", -MASK_LIVE_G0, "Register g0 is fixed with a zero value" }, \ +{"broken-saverestore", MASK_BROKEN_SAVERESTORE, "Enable save/restore bug workarounds" }, \ +{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE, "Disable save/restore bug workarouns" }, #undef ASM_SPEC #define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)" -- 2.30.2