From 14fdec00aa7b9231518b87b7f435b300a2fac381 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 28 Mar 2020 17:51:24 +0000 Subject: [PATCH] add ld/st rev --- openpower/isa/fixedload.mdwn | 70 ++++++++++++++++++++++++++--------- openpower/isa/fixedstore.mdwn | 68 +++++++++++++++++++++++++--------- 2 files changed, 103 insertions(+), 35 deletions(-) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index c4d7e87da..a6651befd 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -1,4 +1,4 @@ -# Load Byte and Zero +# Load Byte and Zero lbz RT,D(RA) @@ -16,7 +16,7 @@ lbzx RT,RA,RB EA <- b + (RB) RT <- [0] * 56 || MEM(EA, 1) -# Load Byte and Zero with Update +# Load Byte and Zero with Update lbzu RT,D(RA) @@ -25,14 +25,14 @@ lbzu RT,D(RA) RA <- EA # Load Byte and Zero with Update Indexed - + lbzux RT,RA,RB EA <- (RA) + (RB) RT <- [0] * 56 || MEM(EA, 1) RA <- EA -# Load Halfword and Zero +# Load Halfword and Zero lhz RT,D(RA) @@ -51,14 +51,14 @@ lhzx RT,RA,RB RT <- [0] * 48 || MEM(EA, 2) # Load Halfword and Zero with Update - + lhzu RT,D(RA) EA <- (RA) + EXTS(D) RT <- [0] * 48 || MEM(EA, 2) RA <- EA -# Load Halfword and Zero with Update Indexed +# Load Halfword and Zero with Update Indexed lhzux RT,RA,RB @@ -66,7 +66,7 @@ lhzux RT,RA,RB RT <- [0] * 48 || MEM(EA, 2) RA <- EA -# Load Halfword Algebraic +# Load Halfword Algebraic lha RT,D(RA) @@ -84,7 +84,7 @@ lhax RT,RA,RB EA <- b + (RB) RT <- EXTS(MEM(EA, 2)) -# Load Halfword Algebraic with Update +# Load Halfword Algebraic with Update lhau RT,D(RA) @@ -92,7 +92,7 @@ lhau RT,D(RA) RT <- EXTS(MEM(EA, 2)) RA <- EA -# Load Halfword Algebraic with Update Indexed +# Load Halfword Algebraic with Update Indexed lhaux RT,RA,RB @@ -126,8 +126,8 @@ lwzu RT,D(RA) RT <- [0]*32 || MEM(EA, 4) RA <- EA -# Load Word and Zero with Update Indexed - +# Load Word and Zero with Update Indexed + lwzux RT,RA,RB EA <- (RA) + (RB) @@ -152,7 +152,7 @@ lwax RT,RA,RB EA <- b + (RB) RT <- EXTS(MEM(EA, 4)) -# Load Word Algebraic with Update Indexed +# Load Word Algebraic with Update Indexed lwaux RT,RA,RB @@ -160,7 +160,7 @@ lwaux RT,RA,RB RT <- EXTS(MEM(EA, 4)) RA <- EA -# Load Doubleword +# Load Doubleword ld RT,DS(RA) @@ -169,7 +169,7 @@ ld RT,DS(RA) EA <- b + EXTS(DS || 0b00) RT <- MEM(EA, 8) -# Load Doubleword Indexed +# Load Doubleword Indexed ldx RT,RA,RB @@ -178,7 +178,7 @@ ldx RT,RA,RB EA <- b + (RB) RT <- MEM(EA, 8) -# Load Doubleword with Update Indexed +# Load Doubleword with Update Indexed ldu RT,DS(RA) @@ -186,8 +186,8 @@ ldu RT,DS(RA) RT <- MEM(EA, 8) RA <- EA -# Load Doubleword with Update Indexed - +# Load Doubleword with Update Indexed + ldux RT,RA,RB EA <- (RA) + (RB) @@ -202,3 +202,39 @@ lq RTp,DQ(RA) else b <- (RA) EA <- b + EXTS(DQ || 0b0000) RTp <- MEM(EA, 16) + +# Load Halfword Byte-Reverse Indexed + +lhbrx RT,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + load_data <- MEM(EA, 2) + RT <- [0]*48 || load_data[8:15] || load_data[0:7] + +# Load Word Byte-Reverse Indexed + +lwbrx RT,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + load_data <- MEM(EA, 4) + RT <- [0] * 32 || load_data[24:31] || load_data[16:23] + || load_data[8:15] || load_data[0:7] + +# Load Doubleword Byte-Reverse Indexed + +ldbrx RT,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + load_data <- MEM(EA, 8) + RT <- load_data[56:63] || load_data[48:55] + || load_data[40:47 || load_data[32:39] + || load_data[24:31 || load_data[16:23] + || load_data[8:15 || load_data[0:7] + + diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn index 99392326c..41e1a931e 100644 --- a/openpower/isa/fixedstore.mdwn +++ b/openpower/isa/fixedstore.mdwn @@ -1,4 +1,4 @@ -# Store Byte +# Store Byte stb RS,D(RA) @@ -7,7 +7,7 @@ stb RS,D(RA) EA <- b + EXTS(D) MEM(EA, 1) <- (RS)[56:63] -# Store Byte Indexed +# Store Byte Indexed stbx RS,RA,RB @@ -16,7 +16,7 @@ stbx RS,RA,RB EA <- b + (RB) MEM(EA, 1) <- (RS)[56:63] -# Store Byte with Update +# Store Byte with Update stbu RS,D(RA) @@ -24,14 +24,14 @@ stbu RS,D(RA) MEM(EA, 1) <- (RS)[56:63] RA <- EA -# Store Byte with Update Indexed +# Store Byte with Update Indexed stbux RS,RA,RB EA <- (RA) + (RB) MEM(EA, 1) <- (RS)[56:63] RA <- EA -# Store Halfword +# Store Halfword sth RS,D(RA) @@ -40,7 +40,7 @@ sth RS,D(RA) EA <- b + EXTS(D) MEM(EA, 2) <- (RS)[48:63] -# Store Halfword Indexed +# Store Halfword Indexed sthx RS,RA,RB @@ -57,8 +57,8 @@ sthu RS,D(RA) MEM(EA, 2) <- (RS)[48:63] RA <- EA -# Store Halfword with Update Indexed - +# Store Halfword with Update Indexed + sthux RS,RA,RB EA <- (RA) + (RB) @@ -67,23 +67,23 @@ sthux RS,RA,RB # Store Word -stw RS,D(RA) +stw RS,D(RA) if RA = 0 then b <- 0 else b <- (RA) EA <- b + EXTS(D) MEM(EA, 4) <- (RS)[32:63] -# Store Word Indexed +# Store Word Indexed -stwx RS,RA,RB +stwx RS,RA,RB if RA = 0 then b <- 0 else b <- (RA) EA <- b + (RB) MEM(EA, 4) <- (RS)[32:63] -# Store Word with Update +# Store Word with Update stwu RS,D(RA) @@ -91,15 +91,15 @@ stwu RS,D(RA) MEM(EA, 4) <- (RS) 32:63 RA <- EA -# Store Word with Update Indexed +# Store Word with Update Indexed -stwux RS,RA,RB +stwux RS,RA,RB EA <- (RA) + (RB) MEM(EA, 4) <- (RS) 32:63 RA <- EA -# Store Doubleword +# Store Doubleword std RS,DS(RA) @@ -108,7 +108,7 @@ std RS,DS(RA) EA <- b + EXTS(DS || 0b00) MEM(EA, 8) <- (RS) -# Store Doubleword Indexed +# Store Doubleword Indexed stdx RS,RA,RB @@ -117,7 +117,7 @@ stdx RS,RA,RB EA <- b + (RB) MEM(EA, 8) <- (RS) -# Store Doubleword with Update +# Store Doubleword with Update stdu RS,DS(RA) @@ -125,7 +125,7 @@ EA <- (RA) + EXTS(DS || 0b00) MEM(EA, 8) <- (RS) RA <- EA -Store Doubleword with Update Indexed +Store Doubleword with Update Indexed stdux RS,RA,RB @@ -142,3 +142,35 @@ stq RSp,DS(RA) EA <- b + EXTS(DS || 0b00) MEM(EA, 16) <- RSp +# Store Halfword Byte-Reverse Indexed + +sthbrx RS,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55] + +# Store Word Byte-Reverse Indexed + +stwbrx RS,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + MEM(EA, 4) <- (RS)[56:63] || (RS)[48:55] || (RS)[40:47] + ||(RS)[32:39] + +# Store Doubleword Byte-Reverse Indexed + +stdbrx RS,RA,RB + + if RA = 0 then b <- 0 + else b <- (RA) + EA <- b + (RB) + MEM(EA, 8) <- (RS) [56:63] || (RS)48:55] + || (RS)[40:47] || (RS)[32:39] + || (RS)[24:31] || (RS)[16:23] + || (RS)[8:15] || (RS)[0:7] + + -- 2.30.2