From 152dc4e13fc8d1cf126b2da63b76366a017ebd31 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Tue, 12 May 2020 12:12:39 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 304] Define minimum viable interface
 set for 180nm ASIC

---
 16/4127b71a68e5b28a17dbab9f27a50510393da5 | 65 +++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 16/4127b71a68e5b28a17dbab9f27a50510393da5

diff --git a/16/4127b71a68e5b28a17dbab9f27a50510393da5 b/16/4127b71a68e5b28a17dbab9f27a50510393da5
new file mode 100644
index 0000000..19ef4aa
--- /dev/null
+++ b/16/4127b71a68e5b28a17dbab9f27a50510393da5
@@ -0,0 +1,65 @@
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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Tue, 12 May 2020 12:12:39 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-304-13-QeaiztsorL@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 304] Define minimum viable interface set for
+ 180nm ASIC
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-- 
2.30.2