From 154d3d3b04d054afc9cd4c6d455ddf932d412191 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 11:23:27 +0200 Subject: [PATCH] liteeth: pep8 (E265) --- misoclib/com/liteeth/core/arp/__init__.py | 14 ++++++++++---- misoclib/com/liteeth/core/etherbone/packet.py | 8 ++++++-- misoclib/com/liteeth/core/etherbone/probe.py | 4 +++- misoclib/com/liteeth/core/etherbone/record.py | 11 ++++++++--- misoclib/com/liteeth/core/etherbone/wishbone.py | 3 ++- misoclib/com/liteeth/core/icmp/__init__.py | 12 +++++++++--- misoclib/com/liteeth/core/ip/__init__.py | 8 ++++++-- misoclib/com/liteeth/core/ip/checksum.py | 4 +++- misoclib/com/liteeth/core/tty/__init__.py | 8 ++++++-- misoclib/com/liteeth/core/udp/__init__.py | 8 ++++++-- .../com/liteeth/example_designs/test/test_la.py | 6 ++---- .../com/liteeth/example_designs/test/test_regs.py | 4 ++-- misoclib/com/liteeth/generic/__init__.py | 3 ++- misoclib/com/liteeth/generic/depacketizer.py | 4 +++- misoclib/com/liteeth/generic/dispatcher.py | 4 +++- misoclib/com/liteeth/generic/packetizer.py | 4 +++- misoclib/com/liteeth/mac/core/crc.py | 8 ++++---- misoclib/com/liteeth/mac/core/gap.py | 4 +++- misoclib/com/liteeth/mac/core/last_be.py | 8 ++++++-- misoclib/com/liteeth/mac/core/padding.py | 8 ++++++-- misoclib/com/liteeth/mac/core/preamble.py | 4 ++-- misoclib/com/liteeth/mac/frontend/sram.py | 4 ++-- misoclib/com/liteeth/mac/frontend/wishbone.py | 4 +++- misoclib/com/liteeth/phy/gmii.py | 12 +++++++++--- misoclib/com/liteeth/phy/gmii_mii.py | 12 +++++++++--- misoclib/com/liteeth/phy/loopback.py | 4 +++- misoclib/com/liteeth/phy/mii.py | 12 +++++++++--- misoclib/com/liteeth/phy/sim.py | 2 +- misoclib/com/liteeth/test/common.py | 8 ++++++-- misoclib/com/liteeth/test/model/arp.py | 8 ++++---- misoclib/com/liteeth/test/model/etherbone.py | 4 ++-- misoclib/com/liteeth/test/model/icmp.py | 8 ++++---- misoclib/com/liteeth/test/model/ip.py | 6 +++--- misoclib/com/liteeth/test/model/mac.py | 8 ++++---- misoclib/com/liteeth/test/model/udp.py | 8 ++++---- 35 files changed, 158 insertions(+), 79 deletions(-) diff --git a/misoclib/com/liteeth/core/arp/__init__.py b/misoclib/com/liteeth/core/arp/__init__.py index 5d010a1b..e564248b 100644 --- a/misoclib/com/liteeth/core/arp/__init__.py +++ b/misoclib/com/liteeth/core/arp/__init__.py @@ -24,7 +24,9 @@ class LiteEthARPTX(Module): def __init__(self, mac_address, ip_address): self.sink = sink = Sink(_arp_table_layout) self.source = source = Source(eth_mac_description(8)) - ### + + # # # + self.submodules.packetizer = packetizer = LiteEthARPPacketizer() counter = Counter(max=max(arp_header_len, eth_min_len)) @@ -88,7 +90,9 @@ class LiteEthARPRX(Module): def __init__(self, mac_address, ip_address): self.sink = sink = Sink(eth_mac_description(8)) self.source = source = Source(_arp_table_layout) - ### + + # # # + self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer() self.comb += Record.connect(sink, depacketizer.sink) @@ -139,12 +143,14 @@ class LiteEthARPRX(Module): class LiteEthARPTable(Module): def __init__(self, clk_freq, max_requests=8): self.sink = sink = Sink(_arp_table_layout) # from arp_rx - self.source = source = Source(_arp_table_layout) # to arp_tx + self.source = source = Source(_arp_table_layout) # to arp_tx # Request/Response interface self.request = request = Sink(arp_table_request_layout) self.response = response = Source(arp_table_response_layout) - ### + + # # # + request_timeout = Timeout(clk_freq//10) request_counter = Counter(max=max_requests) request_pending = FlipFlop() diff --git a/misoclib/com/liteeth/core/etherbone/packet.py b/misoclib/com/liteeth/core/etherbone/packet.py index fa8d76a3..5f5155f3 100644 --- a/misoclib/com/liteeth/core/etherbone/packet.py +++ b/misoclib/com/liteeth/core/etherbone/packet.py @@ -17,7 +17,9 @@ class LiteEthEtherbonePacketTX(Module): def __init__(self, udp_port): self.sink = sink = Sink(eth_etherbone_packet_user_description(32)) self.source = source = Source(eth_udp_user_description(32)) - ### + + # # # + self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), @@ -68,7 +70,9 @@ class LiteEthEtherbonePacketRX(Module): def __init__(self): self.sink = sink = Sink(eth_udp_user_description(32)) self.source = source = Source(eth_etherbone_packet_user_description(32)) - ### + + # # # + self.submodules.depacketizer = depacketizer = LiteEthEtherbonePacketDepacketizer() self.comb += Record.connect(sink, depacketizer.sink) diff --git a/misoclib/com/liteeth/core/etherbone/probe.py b/misoclib/com/liteeth/core/etherbone/probe.py index bc25fe37..9e9671f7 100644 --- a/misoclib/com/liteeth/core/etherbone/probe.py +++ b/misoclib/com/liteeth/core/etherbone/probe.py @@ -6,7 +6,9 @@ class LiteEthEtherboneProbe(Module): def __init__(self): self.sink = sink = Sink(eth_etherbone_packet_user_description(32)) self.source = source = Source(eth_etherbone_packet_user_description(32)) - ### + + # # # + self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", sink.ack.eq(1), diff --git a/misoclib/com/liteeth/core/etherbone/record.py b/misoclib/com/liteeth/core/etherbone/record.py index 4171c6f3..e0cfc7fe 100644 --- a/misoclib/com/liteeth/core/etherbone/record.py +++ b/misoclib/com/liteeth/core/etherbone/record.py @@ -26,7 +26,9 @@ class LiteEthEtherboneRecordReceiver(Module): def __init__(self, buffer_depth=256): self.sink = sink = Sink(eth_etherbone_record_description(32)) self.source = source = Source(eth_etherbone_mmap_description(32)) - ### + + # # # + fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True) self.submodules += fifo self.comb += Record.connect(sink, fifo.sink) @@ -98,7 +100,9 @@ class LiteEthEtherboneRecordSender(Module): def __init__(self, buffer_depth=256): self.sink = sink = Sink(eth_etherbone_mmap_description(32)) self.source = source = Source(eth_etherbone_record_description(32)) - ### + + # # # + pbuffer = PacketBuffer(eth_etherbone_mmap_description(32), buffer_depth) self.submodules += pbuffer self.comb += Record.connect(sink, pbuffer.sink) @@ -148,7 +152,8 @@ class LiteEthEtherboneRecord(Module): def __init__(self, endianness="big"): self.sink = sink = Sink(eth_etherbone_packet_user_description(32)) self.source = source = Sink(eth_etherbone_packet_user_description(32)) - ### + + # # # # receive record, decode it and generate mmap stream self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer() diff --git a/misoclib/com/liteeth/core/etherbone/wishbone.py b/misoclib/com/liteeth/core/etherbone/wishbone.py index d6d2b375..fbaf0630 100644 --- a/misoclib/com/liteeth/core/etherbone/wishbone.py +++ b/misoclib/com/liteeth/core/etherbone/wishbone.py @@ -8,7 +8,8 @@ class LiteEthEtherboneWishboneMaster(Module): self.sink = sink = Sink(eth_etherbone_mmap_description(32)) self.source = source = Source(eth_etherbone_mmap_description(32)) self.bus = bus = wishbone.Interface() - ###s + + # # # self.submodules.data = data = FlipFlop(32) self.comb += data.d.eq(bus.dat_r) diff --git a/misoclib/com/liteeth/core/icmp/__init__.py b/misoclib/com/liteeth/core/icmp/__init__.py index 720a377b..379a2086 100644 --- a/misoclib/com/liteeth/core/icmp/__init__.py +++ b/misoclib/com/liteeth/core/icmp/__init__.py @@ -17,7 +17,9 @@ class LiteEthICMPTX(Module): def __init__(self, ip_address): self.sink = sink = Sink(eth_icmp_user_description(8)) self.source = source = Source(eth_ipv4_user_description(8)) - ### + + # # # + self.submodules.packetizer = packetizer = LiteEthICMPPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), @@ -63,7 +65,9 @@ class LiteEthICMPRX(Module): def __init__(self, ip_address): self.sink = sink = Sink(eth_ipv4_user_description(8)) self.source = source = Source(eth_icmp_user_description(8)) - ### + + # # # + self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer() self.comb += Record.connect(sink, depacketizer.sink) @@ -118,7 +122,9 @@ class LiteEthICMPEcho(Module): def __init__(self): self.sink = sink = Sink(eth_icmp_user_description(8)) self.source = source = Source(eth_icmp_user_description(8)) - ### + + # # # + self.submodules.buffer = PacketBuffer(eth_icmp_user_description(8), 128, 2) self.comb += [ Record.connect(sink, self.buffer.sink), diff --git a/misoclib/com/liteeth/core/ip/__init__.py b/misoclib/com/liteeth/core/ip/__init__.py index 553f131c..baa4d656 100644 --- a/misoclib/com/liteeth/core/ip/__init__.py +++ b/misoclib/com/liteeth/core/ip/__init__.py @@ -20,7 +20,9 @@ class LiteEthIPTX(Module): self.sink = sink = Sink(eth_ipv4_user_description(8)) self.source = source = Source(eth_mac_description(8)) self.target_unreachable = Signal() - ### + + # # # + self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True) self.comb += [ checksum.ce.eq(sink.stb & sink.sop), @@ -108,7 +110,9 @@ class LiteEthIPRX(Module): def __init__(self, mac_address, ip_address): self.sink = sink = Sink(eth_mac_description(8)) self.source = source = Source(eth_ipv4_user_description(8)) - ### + + # # # + self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer() self.comb += Record.connect(sink, depacketizer.sink) diff --git a/misoclib/com/liteeth/core/ip/checksum.py b/misoclib/com/liteeth/core/ip/checksum.py index 7ad77b96..dce3e014 100644 --- a/misoclib/com/liteeth/core/ip/checksum.py +++ b/misoclib/com/liteeth/core/ip/checksum.py @@ -9,7 +9,9 @@ class LiteEthIPV4Checksum(Module): self.header = Signal(ipv4_header_len*8) self.value = Signal(16) self.done = Signal() - ### + + # # # + s = Signal(17) r = Signal(17) n_cycles = 0 diff --git a/misoclib/com/liteeth/core/tty/__init__.py b/misoclib/com/liteeth/core/tty/__init__.py index 4a0917b3..d88d7273 100644 --- a/misoclib/com/liteeth/core/tty/__init__.py +++ b/misoclib/com/liteeth/core/tty/__init__.py @@ -6,7 +6,9 @@ class LiteEthTTYTX(Module): def __init__(self, ip_address, udp_port, fifo_depth=None): self.sink = sink = Sink(eth_tty_description(8)) self.source = source = Source(eth_udp_user_description(8)) - ### + + # # # + if fifo_depth is None: self.comb += [ source.stb.eq(sink.stb), @@ -64,7 +66,9 @@ class LiteEthTTYRX(Module): def __init__(self, ip_address, udp_port, fifo_depth=None): self.sink = sink = Sink(eth_udp_user_description(8)) self.source = source = Source(eth_tty_description(8)) - ### + + # # # + valid = Signal() self.comb += valid.eq( (sink.ip_address == ip_address) & diff --git a/misoclib/com/liteeth/core/udp/__init__.py b/misoclib/com/liteeth/core/udp/__init__.py index f6a1dfdf..60122ea6 100644 --- a/misoclib/com/liteeth/core/udp/__init__.py +++ b/misoclib/com/liteeth/core/udp/__init__.py @@ -18,7 +18,9 @@ class LiteEthUDPTX(Module): def __init__(self, ip_address): self.sink = sink = Sink(eth_udp_user_description(8)) self.source = source = Source(eth_ipv4_user_description(8)) - ### + + # # # + self.submodules.packetizer = packetizer = LiteEthUDPPacketizer() self.comb += [ packetizer.sink.stb.eq(sink.stb), @@ -64,7 +66,9 @@ class LiteEthUDPRX(Module): def __init__(self, ip_address): self.sink = sink = Sink(eth_ipv4_user_description(8)) self.source = source = Source(eth_udp_user_description(8)) - ### + + # # # + self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer() self.comb += Record.connect(sink, depacketizer.sink) diff --git a/misoclib/com/liteeth/example_designs/test/test_la.py b/misoclib/com/liteeth/example_designs/test/test_la.py index 1a4dc169..674cbca1 100644 --- a/misoclib/com/liteeth/example_designs/test/test_la.py +++ b/misoclib/com/liteeth/example_designs/test/test_la.py @@ -7,8 +7,7 @@ def main(wb): wb.open() regs = wb.regs - ### - + # # # conditions = {} la.configure_term(port=0, cond=conditions) la.configure_sum("term") @@ -20,6 +19,5 @@ def main(wb): la.upload() la.save("dump.vcd") - - ### + # # # wb.close() diff --git a/misoclib/com/liteeth/example_designs/test/test_regs.py b/misoclib/com/liteeth/example_designs/test/test_regs.py index 0050fcaa..44f6700a 100644 --- a/misoclib/com/liteeth/example_designs/test/test_regs.py +++ b/misoclib/com/liteeth/example_designs/test/test_regs.py @@ -1,12 +1,12 @@ def main(wb): wb.open() regs = wb.regs - ### + # # # print("sysid : 0x{:04x}".format(regs.identifier_sysid.read())) print("revision : 0x{:04x}".format(regs.identifier_revision.read())) print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000))) SRAM_BASE = 0x02000000 wb.write(SRAM_BASE, [i for i in range(64)]) print(wb.read(SRAM_BASE, 64)) - ### + # # # wb.close() diff --git a/misoclib/com/liteeth/generic/__init__.py b/misoclib/com/liteeth/generic/__init__.py index 1c549828..db1aea0f 100644 --- a/misoclib/com/liteeth/generic/__init__.py +++ b/misoclib/com/liteeth/generic/__init__.py @@ -68,7 +68,8 @@ class PacketBuffer(Module): self.sink = sink = Sink(description) self.source = source = Source(description) - ### + # # # + sink_status = EndpointPacketStatus(self.sink) source_status = EndpointPacketStatus(self.source) self.submodules += sink_status, source_status diff --git a/misoclib/com/liteeth/generic/depacketizer.py b/misoclib/com/liteeth/generic/depacketizer.py index 49d1cf80..85dec05b 100644 --- a/misoclib/com/liteeth/generic/depacketizer.py +++ b/misoclib/com/liteeth/generic/depacketizer.py @@ -16,7 +16,9 @@ class LiteEthDepacketizer(Module): self.sink = sink = Sink(sink_description) self.source = source = Source(source_description) self.header = Signal(header_length*8) - ### + + # # # + dw = flen(sink.data) header_words = (header_length*8)//dw diff --git a/misoclib/com/liteeth/generic/dispatcher.py b/misoclib/com/liteeth/generic/dispatcher.py index 3f88cff0..c11a41ac 100644 --- a/misoclib/com/liteeth/generic/dispatcher.py +++ b/misoclib/com/liteeth/generic/dispatcher.py @@ -14,7 +14,9 @@ class Dispatcher(Module): self.sel = Signal(len(sinks)) else: self.sel = Signal(max=len(sinks)) - ### + + # # # + sop = Signal() self.comb += sop.eq(source.stb & source.sop) sel = Signal(flen(self.sel)) diff --git a/misoclib/com/liteeth/generic/packetizer.py b/misoclib/com/liteeth/generic/packetizer.py index 8ad2bf15..2088486a 100644 --- a/misoclib/com/liteeth/generic/packetizer.py +++ b/misoclib/com/liteeth/generic/packetizer.py @@ -16,7 +16,9 @@ class LiteEthPacketizer(Module): self.sink = sink = Sink(sink_description) self.source = source = Source(source_description) self.header = Signal(header_length*8) - ### + + # # # + dw = flen(self.sink.data) header_reg = Signal(header_length*8) diff --git a/misoclib/com/liteeth/mac/core/crc.py b/misoclib/com/liteeth/mac/core/crc.py index 5f0996ab..d3549791 100644 --- a/misoclib/com/liteeth/mac/core/crc.py +++ b/misoclib/com/liteeth/mac/core/crc.py @@ -31,7 +31,7 @@ class LiteEthMACCRCEngine(Module): self.last = Signal(width) self.next = Signal(width) - ### + # # # def _optimize_eq(l): """ @@ -101,7 +101,7 @@ class LiteEthMACCRC32(Module): self.value = Signal(self.width) self.error = Signal() - ### + # # # self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom) reg = Signal(self.width, reset=self.init) @@ -137,7 +137,7 @@ class LiteEthMACCRCInserter(Module): self.source = source = Source(description) self.busy = Signal() - ### + # # # dw = flen(sink.data) crc = crc_class(dw) @@ -218,7 +218,7 @@ class LiteEthMACCRCChecker(Module): self.source = source = Source(description) self.busy = Signal() - ### + # # # dw = flen(sink.data) crc = crc_class(dw) diff --git a/misoclib/com/liteeth/mac/core/gap.py b/misoclib/com/liteeth/mac/core/gap.py index 07620113..d4caf3c6 100644 --- a/misoclib/com/liteeth/mac/core/gap.py +++ b/misoclib/com/liteeth/mac/core/gap.py @@ -6,7 +6,9 @@ class LiteEthMACGap(Module): def __init__(self, dw, ack_on_gap=False): self.sink = sink = Sink(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw)) - ### + + # # # + gap = math.ceil(eth_interpacket_gap/(dw//8)) self.submodules.counter = counter = Counter(max=gap) diff --git a/misoclib/com/liteeth/mac/core/last_be.py b/misoclib/com/liteeth/mac/core/last_be.py index 200c2cd2..29844f38 100644 --- a/misoclib/com/liteeth/mac/core/last_be.py +++ b/misoclib/com/liteeth/mac/core/last_be.py @@ -6,7 +6,9 @@ class LiteEthMACTXLastBE(Module): def __init__(self, dw): self.sink = sink = Sink(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw)) - ### + + # # # + ongoing = Signal() self.sync += \ If(sink.stb & sink.ack, @@ -29,7 +31,9 @@ class LiteEthMACRXLastBE(Module): def __init__(self, dw): self.sink = sink = Sink(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw)) - ### + + # # # + self.comb += [ source.stb.eq(sink.stb), source.sop.eq(sink.sop), diff --git a/misoclib/com/liteeth/mac/core/padding.py b/misoclib/com/liteeth/mac/core/padding.py index 54003288..bb41cd6a 100644 --- a/misoclib/com/liteeth/mac/core/padding.py +++ b/misoclib/com/liteeth/mac/core/padding.py @@ -6,7 +6,9 @@ class LiteEthMACPaddingInserter(Module): def __init__(self, dw, packet_min_length): self.sink = sink = Sink(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw)) - ### + + # # # + packet_min_data = math.ceil(packet_min_length/(dw/8)) self.submodules.counter = counter = Counter(max=eth_mtu) @@ -42,7 +44,9 @@ class LiteEthMACPaddingChecker(Module): def __init__(self, dw, packet_min_length): self.sink = sink = Sink(eth_phy_description(dw)) self.source = source = Source(eth_phy_description(dw)) - ### + + # # # + # XXX see if we should drop the packet when # payload size < minimum ethernet payload size self.comb += Record.connect(sink, source) diff --git a/misoclib/com/liteeth/mac/core/preamble.py b/misoclib/com/liteeth/mac/core/preamble.py index f82f0787..2854fab9 100644 --- a/misoclib/com/liteeth/mac/core/preamble.py +++ b/misoclib/com/liteeth/mac/core/preamble.py @@ -7,7 +7,7 @@ class LiteEthMACPreambleInserter(Module): self.sink = Sink(eth_phy_description(dw)) self.source = Source(eth_phy_description(dw)) - ### + # # # preamble = Signal(64, reset=eth_preamble) cnt_max = (64//dw)-1 @@ -57,7 +57,7 @@ class LiteEthMACPreambleChecker(Module): self.sink = Sink(eth_phy_description(dw)) self.source = Source(eth_phy_description(dw)) - ### + # # # preamble = Signal(64, reset=eth_preamble) cnt_max = (64//dw) - 1 diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py index 34ae2a82..3a6a8c29 100644 --- a/misoclib/com/liteeth/mac/frontend/sram.py +++ b/misoclib/com/liteeth/mac/frontend/sram.py @@ -20,7 +20,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR): self.ev.available = EventSourceLevel() self.ev.finalize() - ### + # # # # packet dropped if no slot available sink.ack.reset = 1 @@ -133,7 +133,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR): self.ev.done = EventSourcePulse() self.ev.finalize() - ### + # # # # command fifo fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots) diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/mac/frontend/wishbone.py index 05347806..5b9d5563 100644 --- a/misoclib/com/liteeth/mac/frontend/wishbone.py +++ b/misoclib/com/liteeth/mac/frontend/wishbone.py @@ -11,7 +11,9 @@ class LiteEthMACWishboneInterface(Module, AutoCSR): self.sink = Sink(eth_phy_description(dw)) self.source = Source(eth_phy_description(dw)) self.bus = wishbone.Interface() - ### + + # # # + # storage in SRAM sram_depth = buffer_depth//(dw//8) self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) diff --git a/misoclib/com/liteeth/phy/gmii.py b/misoclib/com/liteeth/phy/gmii.py index a39453b4..c181a380 100644 --- a/misoclib/com/liteeth/phy/gmii.py +++ b/misoclib/com/liteeth/phy/gmii.py @@ -7,7 +7,9 @@ from misoclib.com.liteeth.generic import * class LiteEthPHYGMIITX(Module): def __init__(self, pads, pads_register): self.sink = sink = Sink(eth_phy_description(8)) - ### + + # # # + if hasattr(pads, "tx_er"): self.sync += pads.tx_er.eq(0) pads_eq = [ @@ -24,7 +26,9 @@ class LiteEthPHYGMIITX(Module): class LiteEthPHYGMIIRX(Module): def __init__(self, pads): self.source = source = Source(eth_phy_description(8)) - ### + + # # # + dv_d = Signal() self.sync += dv_d.eq(pads.dv) @@ -45,7 +49,9 @@ class LiteEthPHYGMIIRX(Module): class LiteEthPHYGMIICRG(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): self._reset = CSRStorage() - ### + + # # # + self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() diff --git a/misoclib/com/liteeth/phy/gmii_mii.py b/misoclib/com/liteeth/phy/gmii_mii.py index 10b17f79..c147f56f 100644 --- a/misoclib/com/liteeth/phy/gmii_mii.py +++ b/misoclib/com/liteeth/phy/gmii_mii.py @@ -21,7 +21,9 @@ rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)] class LiteEthPHYGMIIMIITX(Module): def __init__(self, pads, mode): self.sink = sink = Sink(eth_phy_description(8)) - ### + + # # # + gmii_tx_pads = Record(tx_pads_layout) gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False) self.submodules += gmii_tx @@ -55,7 +57,9 @@ class LiteEthPHYGMIIMIITX(Module): class LiteEthPHYGMIIMIIRX(Module): def __init__(self, pads, mode): self.source = source = Source(eth_phy_description(8)) - ### + + # # # + pads_d = Record(rx_pads_layout) self.sync += [ pads_d.dv.eq(pads.dv), @@ -82,7 +86,9 @@ class LiteEthGMIIMIIClockCounter(Module, AutoCSR): def __init__(self): self._reset = CSRStorage() self._value = CSRStatus(32) - ### + + # # # + counter = RenameClockDomains(Counter(32), "eth_rx") self.submodules += counter self.comb += [ diff --git a/misoclib/com/liteeth/phy/loopback.py b/misoclib/com/liteeth/phy/loopback.py index aa046224..1d214008 100644 --- a/misoclib/com/liteeth/phy/loopback.py +++ b/misoclib/com/liteeth/phy/loopback.py @@ -5,7 +5,9 @@ from misoclib.com.liteeth.generic import * class LiteEthPHYLoopbackCRG(Module, AutoCSR): def __init__(self): self._reset = CSRStorage() - ### + + # # # + self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() self.comb += [ diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py index 8c5659f2..52ac0d8b 100644 --- a/misoclib/com/liteeth/phy/mii.py +++ b/misoclib/com/liteeth/phy/mii.py @@ -10,7 +10,9 @@ def converter_description(dw): class LiteEthPHYMIITX(Module): def __init__(self, pads, pads_register=True): self.sink = sink = Sink(eth_phy_description(8)) - ### + + # # # + if hasattr(pads, "tx_er"): self.sync += pads.tx_er.eq(0) converter = Converter(converter_description(8), converter_description(4)) @@ -34,7 +36,9 @@ class LiteEthPHYMIITX(Module): class LiteEthPHYMIIRX(Module): def __init__(self, pads): self.source = source = Source(eth_phy_description(8)) - ### + + # # # + sop = FlipFlop(reset=1) self.submodules += sop @@ -59,7 +63,9 @@ class LiteEthPHYMIIRX(Module): class LiteEthPHYMIICRG(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset): self._reset = CSRStorage() - ### + + # # # + if hasattr(clock_pads, "phy"): self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy) diff --git a/misoclib/com/liteeth/phy/sim.py b/misoclib/com/liteeth/phy/sim.py index 3c8268ff..d4067b3e 100644 --- a/misoclib/com/liteeth/phy/sim.py +++ b/misoclib/com/liteeth/phy/sim.py @@ -8,7 +8,7 @@ class LiteEthPHYSimCRG(Module, AutoCSR): def __init__(self): self._reset = CSRStorage() - ### + # # # self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() diff --git a/misoclib/com/liteeth/test/common.py b/misoclib/com/liteeth/test/common.py index 69657574..4f72b6fa 100644 --- a/misoclib/com/liteeth/test/common.py +++ b/misoclib/com/liteeth/test/common.py @@ -86,7 +86,9 @@ class PacketStreamer(Module): def __init__(self, description, last_be=None): self.source = Source(description) self.last_be = last_be - ### + + # # # + self.packets = [] self.packet = Packet() self.packet.done = True @@ -130,7 +132,9 @@ class PacketStreamer(Module): class PacketLogger(Module): def __init__(self, description): self.sink = Sink(description) - ### + + # # # + self.packet = Packet() def receive(self): diff --git a/misoclib/com/liteeth/test/model/arp.py b/misoclib/com/liteeth/test/model/arp.py index 4cee649c..88f39b9e 100644 --- a/misoclib/com/liteeth/test/model/arp.py +++ b/misoclib/com/liteeth/test/model/arp.py @@ -130,12 +130,12 @@ if __name__ == "__main__": packet = ARPPacket(packet) # check decoding packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_request_infos) # check encoding packet.encode() packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_request_infos) # ARP Reply @@ -144,12 +144,12 @@ if __name__ == "__main__": packet = ARPPacket(packet) # check decoding packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_reply_infos) # check encoding packet.encode() packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_reply_infos) print("arp errors " + str(errors)) diff --git a/misoclib/com/liteeth/test/model/etherbone.py b/misoclib/com/liteeth/test/model/etherbone.py index fc43c2ef..1ad51b2c 100644 --- a/misoclib/com/liteeth/test/model/etherbone.py +++ b/misoclib/com/liteeth/test/model/etherbone.py @@ -349,9 +349,9 @@ if __name__ == "__main__": packet.nr = 0 packet.pr = 0 packet.pf = 0 - #print(packet) + # print(packet) packet.encode() - #print(packet) + # print(packet) # Send packet over UDP to check against Wireshark dissector import socket diff --git a/misoclib/com/liteeth/test/model/icmp.py b/misoclib/com/liteeth/test/model/icmp.py index bab9b334..e293101f 100644 --- a/misoclib/com/liteeth/test/model/icmp.py +++ b/misoclib/com/liteeth/test/model/icmp.py @@ -89,17 +89,17 @@ if __name__ == "__main__": # ICMP packet packet = MACPacket(ping_request) packet.decode_remove_header() - #print(packet) + # print(packet) packet = IPPacket(packet) packet.decode() - #print(packet) + # print(packet) packet = ICMPPacket(packet) packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, ping_request_infos) packet.encode() packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, ping_request_infos) print("icmp errors " + str(errors)) diff --git a/misoclib/com/liteeth/test/model/ip.py b/misoclib/com/liteeth/test/model/ip.py index 4fe8be47..802815a1 100644 --- a/misoclib/com/liteeth/test/model/ip.py +++ b/misoclib/com/liteeth/test/model/ip.py @@ -135,19 +135,19 @@ if __name__ == "__main__": # UDP packet packet = MACPacket(udp) packet.decode_remove_header() - #print(packet) + # print(packet) packet = IPPacket(packet) # check decoding errors += not packet.check_checksum() packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, {}) # check encoding packet.encode() packet.insert_checksum() errors += not packet.check_checksum() packet.decode() - #print(packet) + # print(packet) errors += verify_packet(packet, {}) print("ip errors " + str(errors)) diff --git a/misoclib/com/liteeth/test/model/mac.py b/misoclib/com/liteeth/test/model/mac.py index 41d41ab9..f61502d4 100644 --- a/misoclib/com/liteeth/test/model/mac.py +++ b/misoclib/com/liteeth/test/model/mac.py @@ -136,20 +136,20 @@ if __name__ == "__main__": errors = 0 packet = MACPacket(arp_request) packet.decode_remove_header() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_request_infos) packet.encode_header() packet.decode_remove_header() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_request_infos) - #print(packet) + # print(packet) packet = MACPacket(arp_reply) packet.decode_remove_header() errors += verify_packet(packet, arp_reply_infos) packet.encode_header() packet.decode_remove_header() - #print(packet) + # print(packet) errors += verify_packet(packet, arp_reply_infos) print("mac errors " + str(errors)) diff --git a/misoclib/com/liteeth/test/model/udp.py b/misoclib/com/liteeth/test/model/udp.py index fa61ccd6..22fecb90 100644 --- a/misoclib/com/liteeth/test/model/udp.py +++ b/misoclib/com/liteeth/test/model/udp.py @@ -100,19 +100,19 @@ if __name__ == "__main__": # UDP packet packet = MACPacket(udp) packet.decode_remove_header() - #print(packet) + # print(packet) packet = IPPacket(packet) packet.decode() - #print(packet) + # print(packet) packet = UDPPacket(packet) packet.decode() - #print(packet) + # print(packet) if packet.length != (len(packet)+udp_header_len): errors += 1 errors += verify_packet(packet, udp_infos) packet.encode() packet.decode() - #print(packet) + # print(packet) if packet.length != (len(packet)+udp_header_len): errors += 1 errors += verify_packet(packet, udp_infos) -- 2.30.2