From 15566183a64ef3f9940962a3b08b1c3469c98566 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 9 Dec 2010 09:36:17 -0800 Subject: [PATCH] i965: Add support for gen6 constant-index constant loading. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 +++++++++- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 -- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index b20d88280f9..93ccdde44b5 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1708,9 +1708,13 @@ void brw_dp_READ_4_vs(struct brw_compile *p, GLuint location, GLuint bind_table_index) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; GLuint msg_reg_nr = 1; + if (intel->gen >= 6) + location /= 16; + /* Setup MRF[1] with location/offset into const buffer */ brw_push_insn_state(p); brw_set_compression_control(p, BRW_COMPRESSION_NONE); @@ -1729,7 +1733,11 @@ void brw_dp_READ_4_vs(struct brw_compile *p, insn->header.mask_control = BRW_MASK_DISABLE; brw_set_dest(p, insn, dest); - brw_set_src0(insn, brw_null_reg()); + if (intel->gen >= 6) { + brw_set_src0(insn, brw_message_reg(msg_reg_nr)); + } else { + brw_set_src0(insn, brw_null_reg()); + } brw_set_dp_read_message(p->brw, insn, diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index b7771e66d59..eccc6b7584e 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1072,8 +1072,6 @@ get_constant(struct brw_vs_compile *c, assert(argIndex < 3); - assert(c->func.brw->intel.gen < 6); /* FINISHME */ - if (c->current_const[argIndex].index != src->Index) { /* Keep track of the last constant loaded in this slot, for reuse. */ c->current_const[argIndex].index = src->Index; -- 2.30.2