From 155a5c989676db9b64cf768ce116505aa8103ee5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Jun 2020 16:21:05 +0100 Subject: [PATCH] more comments --- src/soc/fu/trap/main_stage.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index fc862e18..81cbe8c8 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -139,11 +139,14 @@ class TrapMainStage(PipeModBase): ctrl_tmp.srr1(63 - 46) <= '1'; """ with m.If(should_trap): + # change the PC to trap address 0x700 comb += nia_o.data.eq(0x700) # trap address comb += nia_o.ok.eq(1) + # take a copy of the current MSR in SRR1 comb += msr_copy(srr1_o.data, msr_i) # old MSR comb += srr1_o.data[63-46].eq(1) # XXX which bit? comb += srr1_o.ok.eq(1) + # take a copy of the current PC in SRR0 comb += srr0_o.data.eq(cia_i) # old PC comb += srr0_o.ok.eq(1) -- 2.30.2