From 15615a484ae6b91fa0047e949853109f64c64983 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Nov 2021 14:36:09 +0000 Subject: [PATCH] remove issue_i from core, use i_valid instead to decide when to issue converting core to Pipeline API --- src/soc/simple/core.py | 17 +++++++++++------ src/soc/simple/issuer.py | 6 +----- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 9343081c..a37b9ba4 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -90,16 +90,12 @@ class CoreInput: self.sv_pred_sm = Signal() # TODO: SIMD width self.sv_pred_dm = Signal() # TODO: SIMD width - # issue/valid/busy signalling - self.issue_i = Signal(reset_less=True) - def eq(self, i): self.e.eq(i.e) self.sv_a_nz.eq(i.sv_a_nz) self.state.eq(i.state) self.raw_insn_i.eq(i.raw_insn_i) self.bigendian_i.eq(i.bigendian_i) - self.issue_i.eq(i.issue_i) if not self.svp64_en: return self.sv_rm.eq(i.sv_rm) @@ -309,14 +305,23 @@ class NonProductionCore(ControlBase): with m.If(enable): # operand comes from the *local* decoder comb += fu.oper_i.eq_from(do) - #comb += fu.oper_i.eq_from_execute1(e) - comb += fu.issue_i.eq(self.i.issue_i) + comb += fu.issue_i.eq(1) # issue when input valid comb += busy_o.eq(fu.busy_o) # rdmask, which is for registers, needs to come # from the *main* decoder rdmask = get_rdflags(self.i.e, fu) comb += fu.rdmaskn.eq(~rdmask) + # if instruction is busy, set busy output for core. also + # continue to hold each fu rdmask + for funame, fu in fus.items(): + with m.If(fu.busy_o): + comb += busy_o.eq(fu.busy_o) + # rdmask, which is for registers, needs to come + # from the *main* decoder + rdmask = get_rdflags(self.i.e, fu) + comb += fu.rdmaskn.eq(~rdmask) + # set ready/valid signalling. if busy, means refuse incoming issue comb += self.p.o_ready.eq(~busy_o) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index b5dc3784..7312575d 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -863,7 +863,6 @@ class TestIssuerInternal(Elaboratable): # temporaries core_busy_o = ~core.p.o_ready # core is busy core_ivalid_i = core.p.i_valid # instruction is valid - core_issue_i = core.i.issue_i # instruction is issued insn_type = core.i.e.do.insn_type # instruction MicroOp type with m.FSM(name="exec_fsm"): @@ -872,16 +871,13 @@ class TestIssuerInternal(Elaboratable): with m.State("INSN_START"): comb += exec_insn_o_ready.eq(1) with m.If(exec_insn_i_valid): - comb += core_ivalid_i.eq(1) # instruction is valid - comb += core_issue_i.eq(1) # and issued + comb += core_ivalid_i.eq(1) # instruction is valid/issued sync += sv_changed.eq(0) sync += pc_changed.eq(0) m.next = "INSN_ACTIVE" # move to "wait completion" # instruction started: must wait till it finishes with m.State("INSN_ACTIVE"): - with m.If(insn_type != MicrOp.OP_NOP): - comb += core_ivalid_i.eq(1) # instruction is valid # note changes to PC and SVSTATE with m.If(self.state_nia.wen & (1<