From 1564b440eb1a993664defbdccddc0a71816fb0c4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 19 Jul 2018 12:51:16 +0200 Subject: [PATCH] soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 --- litex/soc/integration/soc_sdram.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 1c9064c2..218ac86b 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -37,6 +37,8 @@ class SoCSDRAM(SoCCore): def __init__(self, platform, clk_freq, l2_size=8192, **kwargs): SoCCore.__init__(self, platform, clk_freq, **kwargs) + if self.cpu_type is not None and self.csr_data_width != 8: + raise NotImplementedError("BIOS supports SDRAM initialization only for csr_data_width=8") self.l2_size = l2_size self._sdram_phy = [] -- 2.30.2