From 158ae534e5fc4778bb663cc513fba38b99578607 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Oct 2022 16:12:06 +0100
Subject: [PATCH] add dsld. (Rc=1) test, make overflow acceptable to
 handle_comparison() in ISACaller

---
 src/openpower/decoder/isa/caller.py       | 10 ++++--
 src/openpower/test/bigint/bigint_cases.py | 39 +++++++++++++++++++++++
 2 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index de6719ad..fd2cdc3f 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1472,7 +1472,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             SO = SelectableInt(1, 0)
         else:
             SO = self.spr['XER'][XER_bits['SO']]
-        log("handle_comparison SO overflow", SO, overflow)
+        log("handle_comparison SO", SO.value,
+                    "overflow", overflow,
+                    "zero", zero.value,
+                    "+ve", positive.value,
+                     "-ve", negative.value)
         # alternative overflow checking (setvl mainly at the moment)
         if overflow is not None and overflow == 1:
             SO = SelectableInt(1, 1)
@@ -2057,8 +2061,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         is_setvl = ins_name in ('svstep', 'setvl')
         if is_setvl:
             result = SelectableInt(result.vl, 64)
-        else:
-            overflow = None  # do not override overflow except in setvl
+        #else:
+        #    overflow = None  # do not override overflow except in setvl
 
         # if there was not an explicit CR0 in the pseudocode, do implicit Rc=1
         if cr0 is None:
diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 9abdce55..bc964562 100644
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -6,6 +6,21 @@ from openpower.decoder.isa.caller import SVP64State
 
 _SHIFT_TEST_RANGE = list(range(-64, 128, 16)) + [1, 63]
 
+def cr_calc(val, ov):
+    XLEN=64
+    msb = (val & (1<<(XLEN-1))) != 0
+    lsbs = (val & ~(1<<(XLEN-1))) != 0
+    crf = 0
+    if val == 0:           # zero
+        crf |= 0b010
+    elif lsbs and not msb: # positive
+        crf |= 0b100
+    elif lsbs and msb: # negative
+        crf |= 0b1000
+    if ov:
+        crf |= 0b0001
+    return crf
+
 
 class BigIntCases(TestAccumulatorBase):
     def case_maddedu(self):
@@ -33,6 +48,30 @@ class BigIntCases(TestAccumulatorBase):
 
     # FIXME: test more divmod2du special cases
 
+    def case_dsld0_(self):
+        prog = Program(list(SVP64Asm(["dsld. 3,4,5,6"])), False)
+        for vals in [(0x0000_0000_0000_0000, 0, 0x0000_0000_0000_0000),
+                     (0x8000_0000_0000_0000, 1, 0x0000_0000_0000_0000),
+                     (0xffff_ffff_ffff_ffff, 1, 0x0000_0000_0000_0001),
+                     (0x0fff_ffff_ffff_fff0, 1, 0x8000_0000_0000_0001),
+                     (0xdfff_ffff_ffff_ffff, 1, 0x8000_0000_0000_0000),
+                    ]:
+            (ra, rb, rc) = vals
+            with self.subTest(ra=ra, rb=rb, rc=rc):
+                gprs = [0] * 32
+                gprs[4] = ra
+                gprs[5] = rb
+                gprs[6] = rc
+                e = ExpectedState(pc=4, int_regs=gprs, crregs=8)
+                v = ra
+                v <<= rb % 64
+                mask = (1 << (rb % 64))-1
+                v |= rc & mask
+                e.intregs[3] = v % 2 ** 64
+                e.intregs[6] = (v >> 64) % 2 ** 64
+                e.crregs[0] = cr_calc(e.intregs[3], ov=e.intregs[6] != 0)
+                self.add_case(prog, gprs, expected=e)
+
     def case_dsld0(self):
         prog = Program(list(SVP64Asm(["dsld 3,4,5,6"])), False)
         for sh in _SHIFT_TEST_RANGE:
-- 
2.30.2