From 15a11f7465b529cabdda8397f9da3a15e8be49f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 12:03:55 +0100 Subject: [PATCH] mention convenience variables --- src/soc/fu/trap/main_stage.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 48dd5ef1..5d29838f 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -49,6 +49,7 @@ class TrapMainStage(PipeModBase): comb = m.d.comb op = self.i.ctx.op + # convenience variables a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia srr0_o, srr1_o = self.o.srr0, self.o.srr1 @@ -155,6 +156,7 @@ class TrapMainStage(PipeModBase): with m.Else(): for stt, end in [(1,12), (13, 60), (61, 64)]: + # TODO a_i not a comb += msr_o.data[stt:end].eq(a[stt:end]) with m.If(a[MSR_PR]): msr_o[MSR_EE].eq(1) @@ -189,9 +191,11 @@ class TrapMainStage(PipeModBase): ctrl_tmp.msr(MSR_DR) <= '1'; end if; """ + # TODO a_i not a, from the convenience variables comb += nia_o.data.eq(br_ext(a[63:1] & 0)) comb += nia_o.ok.eq(1) for stt, end in [(0,16), (22, 27), (31, 64)]: + # TODO b_i not a, look above, the VHDL uses b_in comb += msr_o.data[stt:end].eq(a[stt:end]) with m.If(a[MSR_PR]): msr_o[MSR_EE].eq(1) -- 2.30.2