From 15d027866462b0e2468f4e3c1865035704cdb6ff Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 4 Jun 2021 01:44:39 +0100 Subject: [PATCH] --- openpower/sv/int_fp_mv.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 8e86c8f10..2354e3b5b 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -172,7 +172,16 @@ move a 32-bit float from a GPR to a FPR, just copying bits. Converts the TODO: Rc=1 variants? -TODO: clear statement on evaluation as to whethrer exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the converdion part. the semantics should really be the same as frsp) +TODO: clear statement on evaluation as to whethrer exceptions or flags raised as part of the **FP** conversion (not the int bitcopy part, the conversion part. the semantics should really be the same as frsp) + +v3.0C section 4.6.1 states: + +FPRF is set to the class and sign of the result, except for Invalid Operation Exceptions when VE=1. + + Special Registers Altered: + FPRF FR FI + FX OX UX XX VXSNAN + CR1 (if Rc=1) ### Float load immediate (kinda a variant of `fmvfg`) -- 2.30.2