From 15d4930dc5a7c684477f1122f4481cefadf161a0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 9 Mar 2018 02:39:55 +0000
Subject: [PATCH]

---
 shakti/m_class/pinmux.mdwn | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn
index cc1fbca25..dcdac9758 100644
--- a/shakti/m_class/pinmux.mdwn
+++ b/shakti/m_class/pinmux.mdwn
@@ -18,6 +18,14 @@ optional pull-up and pull-down resistors, in an IDENTICAL fashion to
 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
 
+* Number of wires shall be minimised especially in cases where
+  outputs need to change characteristics of the IO pad (puen, oe)
+* There shall be no short-circuits created by multiple input
+  pins trying to drive the same input function
+* The IO pad shall have pull-up enable, pull-down enable, variable
+  frequency de-bounce, tri-state capability, Open Drain and CMOS
+  Push-Push.
+
 ## Analysis
 
 Questions:
-- 
2.30.2