From 15d86ae36101da78957fe78cce0223e3a6420aae Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 22 Apr 2023 12:03:15 +0100 Subject: [PATCH] whitespace --- openpower/sv/vector_ops.mdwn | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index 67d95d4df..e12e7e669 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -15,20 +15,25 @@ Links: contains pseudocode for sof, sif, sbf * -The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. -Therefore there are not that many cases where *actual* Vector -instructions are needed. If they are, they are more "assistance" -functions. Two traditional Vector instructions were initially -considered (conflictd and vmiota) however they may be synthesised -from existing SVP64 instructions: vmiota may use [[svstep]]. -Details in [[discussion]] +The core Power ISA was designed as scalar: SV provides a level of +abstraction to add variable-length element-independent parallelism. +Therefore there are not that many cases where *actual* Vector instructions +are needed. If they are, they are more "assistance" functions. Two +traditional Vector instructions were initially considered (conflictd and +vmiota) however they may be synthesised from existing SVP64 instructions: +vmiota may use [[svstep]]. Details in [[discussion]] Notes: -* Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU) -* Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations. See [[sv/cr_int_predication]]. +* Instructions suited to 3D GPU workloads (dotproduct, crossproduct, + normalise) are out of scope: this document is for more general-purpose + instructions that underpin and are critical to general-purpose Vector + workloads (including GPU and VPU) +* Instructions related to the adaptation of CRs for use as + predicate masks are covered separately, by crweird operations. + See [[sv/cr_int_predication]]. -# Mask-suited Bitmanipulation +## Mask-suited Bitmanipulation Based on RVV masked set-before-first, set-after-first etc. and Intel and AMD Bitmanip instructions made generalised then @@ -67,7 +72,7 @@ Executable pseudocode demo: [[!inline pages="openpower/sv/bmask.py" quick="yes" raw="yes" ]] ``` -# Carry-lookahead +## Carry-lookahead As a single scalar 32-bit instruction, up to 64 carry-propagation bits may be computed. When the output is then used as a Predicate mask it can @@ -79,9 +84,11 @@ be used to selectively perform the "add carry" of biginteger math, with pseudocode: +``` P = (RA) G = (RB) RT = ((P|G)+G)^P +``` X-Form -- 2.30.2