From 15e877ef22b5ad4dfafdb5baa3a20d0c25e0fc78 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Jun 2020 14:46:25 +0100
Subject: [PATCH] use ALUHelpers in LDSTCompUnit test

---
 .../fu/compunits/test/test_ldst_compunit.py   | 35 ++++++-------------
 src/soc/fu/test/common.py                     | 20 ++++++++++-
 2 files changed, 30 insertions(+), 25 deletions(-)

diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py
index c91b2e5d..67fe0516 100644
--- a/src/soc/fu/compunits/test/test_ldst_compunit.py
+++ b/src/soc/fu/compunits/test/test_ldst_compunit.py
@@ -5,6 +5,7 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase, get_cu_inputs
 
 from soc.fu.compunits.compunits import LDSTFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.fu.test.common import ALUHelpers
 
 
 class LDSTTestRunner(TestRunner):
@@ -22,24 +23,7 @@ class LDSTTestRunner(TestRunner):
         """naming (res) must conform to LDSTFunctionUnit output regspec
         """
 
-        print ("check cu outputs", res)
-        # RT
-        out_reg_valid = yield dec2.e.write_reg.ok
-        if out_reg_valid:
-            write_reg_idx = yield dec2.e.write_reg.data
-            expected = sim.gpr(write_reg_idx).value
-            cu_out = res['o']
-            print(f"expected {expected:x}, actual: {cu_out:x}")
-            self.assertEqual(expected, cu_out, code)
-
-        # RA
-        out_reg_valid = yield dec2.e.write_ea.ok
-        if out_reg_valid:
-            write_reg_idx = yield dec2.e.write_ea.data
-            expected = sim.gpr(write_reg_idx).value
-            cu_out = res['o1']
-            print(f"expected {expected:x}, actual: {cu_out:x}")
-            self.assertEqual(expected, cu_out, code)
+        print ("check cu outputs", code, res)
 
         rc = yield dec2.e.rc.data
         op = yield dec2.e.insn_type
@@ -52,12 +36,15 @@ class LDSTTestRunner(TestRunner):
             self.assertEqual(cridx_ok, 1, code)
             self.assertEqual(cridx, 0, code)
 
-        # CR (CR0-7)
-        if cridx_ok:
-            cr_expected = sim.crl[cridx].get_range().value
-            cr_actual = res['cr_a']
-            print ("CR", cridx, cr_expected, cr_actual)
-            self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+        sim_o = {}
+
+        yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+        yield from ALUHelpers.get_sim_int_o1(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+
+        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+        ALUHelpers.check_int_o(self, res, sim_o, code)
+        ALUHelpers.check_int_o1(self, res, sim_o, code)
 
         # XER.so
         return
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index e61edb48..f663efe1 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -140,10 +140,15 @@ class ALUHelpers:
         else:
             yield alu.p.data_i.full_cr.eq(0)
 
+    def get_int_o1(res, alu, dec2):
+        out_reg_valid = yield dec2.e.write_ea.ok
+        if out_reg_valid:
+            res['o1'] = yield alu.n.data_o.o1.data
+
     def get_int_o(res, alu, dec2):
         out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
-            res['o'] = yield alu.n.data_o.o.data 
+            res['o'] = yield alu.n.data_o.o.data
 
     def get_cr_a(res, alu, dec2):
         cridx_ok = yield dec2.e.write_cr.ok
@@ -173,6 +178,12 @@ class ALUHelpers:
             write_reg_idx = yield dec2.e.write_reg.data
             res['o'] = sim.gpr(write_reg_idx).value
 
+    def get_sim_int_o1(res, sim, dec2):
+        out_reg_valid = yield dec2.e.write_ea.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_ea.data
+            res['o1'] = sim.gpr(write_reg_idx).value
+
     def get_wr_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.write_cr.ok
         if cridx_ok:
@@ -200,6 +211,13 @@ class ALUHelpers:
         if oe and oe_ok:
             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 
+    def check_int_o1(dut, res, sim_o, msg):
+        if 'o1' in res:
+            expected = sim_o['o1']
+            alu_out = res['o1']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
     def check_int_o(dut, res, sim_o, msg):
         if 'o' in res:
             expected = sim_o['o']
-- 
2.30.2