From 1610e1fa216221e6a6c2a8a3c826dd89b4bd80c7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 9 Jan 2022 21:19:39 +0000
Subject: [PATCH] add verilator snoop of LDST request address (to capture
 requests which go through the MMU. current dump only outputs physical
 address: this is the virtual address)

---
 core.vhdl                         |  9 ++++++++-
 core_dummy.vhdl                   |  5 ++++-
 fpga/top-generic.vhdl             |  9 ++++++---
 soc.vhdl                          | 12 +++++++++---
 verilator/microwatt-verilator.cpp | 11 ++++++++++-
 5 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/core.vhdl b/core.vhdl
index f5638c8..a6cad76 100644
--- a/core.vhdl
+++ b/core.vhdl
@@ -46,7 +46,9 @@ entity core is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    insn: out std_ulogic_vector(31 downto 0);
+    ldst_req: out std_ulogic;
+    ldst_addr: out std_ulogic_vector(63 downto 0)
         );
 end core;
 
@@ -446,6 +448,11 @@ begin
     msr_o <= msr;
     insn <= icache_to_decode1.insn;
     nia_req <= icache_to_decode1.valid and fetch1_to_icache.sequential;
+    -- hmmm....
+    ldst_req <= execute1_to_loadstore1.valid;
+    ldst_addr <= std_ulogic_vector(unsigned(execute1_to_loadstore1.addr1) +
+                                   unsigned(execute1_to_loadstore1.addr2))
+                  when execute1_to_loadstore1.valid = '1' else (others => '0');
 
     debug_0: entity work.core_debug
 
diff --git a/core_dummy.vhdl b/core_dummy.vhdl
index 9ceab19..8967bb7 100644
--- a/core_dummy.vhdl
+++ b/core_dummy.vhdl
@@ -45,7 +45,10 @@ entity core is
     -- for verilator debugging
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    msr_o: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
         );
 end core;
 
diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 32bdfce..66c65cc 100644
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -42,8 +42,9 @@ entity toplevel is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
-
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
 	);
 end entity toplevel;
 
@@ -115,7 +116,9 @@ begin
         nia_req           => nia_req,
         nia               => nia,
         msr_o             => msr_o,
-        insn              => insn
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
 	    );
 
 end architecture behaviour;
diff --git a/soc.vhdl b/soc.vhdl
index 2212247..042f224 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -123,7 +123,9 @@ entity soc is
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
     msr_o: out std_ulogic_vector(63 downto 0);
-    insn: out std_ulogic_vector(31 downto 0)
+    insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
 	);
 end entity soc;
 
@@ -278,7 +280,9 @@ architecture behaviour of soc is
         nia_req: out std_ulogic;
         msr_o: out std_ulogic_vector(63 downto 0);
         nia: out std_ulogic_vector(63 downto 0);
-        insn: out std_ulogic_vector(31 downto 0)
+        insn: out std_ulogic_vector(31 downto 0);
+        ldst_req: out std_ulogic;
+        ldst_addr: out std_ulogic_vector(63 downto 0)
         );
     end component;
 begin
@@ -328,7 +332,9 @@ begin
         nia_req           => nia_req,
         nia               => nia,
         msr_o             => msr_o,
-        insn              => insn
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
 	    );
     end generate;
 
diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index b75eb52..8ef758d 100644
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -197,9 +197,18 @@ int main(int argc, char **argv)
 
 #ifdef BRAM_DEBUG
         if (top->nia_req) {
-            fprintf(dump, "pc %8x insn %8x msr %16lx\n",
+            fprintf(dump, "pc %8x insn %8x msr %16lx",
                                 top->nia, top->insn, top->msr_o);
         }
+        if (top->ldst_req) {
+            if (!top->nia_req) {
+                fprintf(dump, "pc %-8s insn %-8s msr %-16s", "", "", "");
+            }
+            fprintf(dump, "    ldst %16lx", top->ldst_addr);
+        }
+        if (top->ldst_req || top->nia_req) {
+            fprintf(dump, "\n");
+        }
         if (top->bram_we) {
             fprintf(dump, "                          " \
                           "wr @ %08x do %16lx sel %02x ",
-- 
2.30.2